Features

• Supported data rates: 1 Mbps, 2 Mbps, and Long Range (500 kbps, 125 kbps)
• TX power: –20 dBm to +7 dBm
• RX sensitivity
  • –97 dBm sensitivity @ 1 Mbps mode
  • –93 dBm sensitivity @ 2 Mbps mode
  • –101 dBm sensitivity @ Long Range 500 kbps mode
  • –103 dBm sensitivity @ Long Range 125 kbps mode
• Power consumption at 3.3 V VBAT input:
  • 6.3 mA TX current @ 0 dBm output power (64 MHz system clock)
  • 5.3 mA RX current @ 1 Mbps (64 MHz system clock)

• Up to 96 MHz clock frequency
• Built-in Memory Protection Unit (MPU) supporting eight programmable regions
• Hardware Floating Point Unit (FPU)
• Built-in Nested Vectored Interrupt Controller (NVIC)
• Non-maskable Interrupt (NMI) input
• Serial Wire Debug (SWD) with 16 breakpoints, two watchpoints, and a debug timestamp counter
• 56 µA/MHz CoreMark running from Flash @ 3.3 V, 64 MHz from HFXO

• 256 KB RAM data memory with retention capabilities
• 8 KB cache RAM instruction memory with retention capabilities
• Stack ROM (including boot ROM and Bluetooth LE Stack)
• 1 MB internal QSPI Flash (512 KB for GR5525IENI, and external Flash for GR5525I0NI)

• 2 x general-purpose DMA engines with six channels and up to 16 programmable request/trigger sources

• 1 x 13-bit Sense ADC with sampling rate of 1 Msps, supporting up to eight external I/O channels and three internal signal channels
• Built-in die temperature and voltage sensors
• Low-power comparator, supporting wakeup from sleep mode

• 4 x UART modules up to 2 Mbps with flow control and IrDA features
• 4 x I2C modules for peripheral communication, up to 3.4 MHz, operating as either Master or Slave
• 2 x I2S interfaces (1 x I2S master interface and 1 x I2S slave interface)
• PDM interface with hardware sampling rate converter
• 1 x 8-bit/16-bit/32-bit SPI master interface and 1 x SPI slave interface for host communication
• 1 x Dual-lane SPI (DSPI) interface for display, with MIPI DBI Type-C support
• 3 x Quad SPI (QSPI) interfaces, up to 48 MHz; supporting direct access via memory mapping when connecting with external NOR Flash

• Complete secure computing engine:
  • AES 128-bit/192-bit/256-bit symmetric encryption (ECB, CBC)
  • Hash-based Message Authentication Code (HMAC-SHA256)
  • Public key cryptography (PKC)
  • True random number generator (TRNG)
• Comprehensive security operation mechanism:
  • Secure boot
  • Encrypted firmware running directly from Flash
  • eFuse for encrypted key storage
  • Differentiate application data key and firmware key, supporting one data key per device/product

• Up to 50 multiplexed I/O pins in total
  • Up to 34 general-purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors
  • Up to eight always-on I/O (AON I/O) pins, supporting wakeup from sleep mode
  • Up to eight mixed signal I/O (MSIO) pins, configurable to be digital/analog signal interfaces

• 2 x 32-bit general-purpose timers
• 1 x dual timer with two programmable 32-bit or 16-bit down counters
• 1 x sleep timer for waking the device up from sleep mode
• 2 x 3-channel PWMs with edge-aligned and center-aligned modes
• 2 x real-time counters (1 x Calendar, 1 x real-time counter)

• On-chip DC-DC to provide RF analog voltage and supply core LDO
• On-chip I/O LDO to provide I/O voltage and supply external components
• Programmable thresholds for brownout detector (BOD)
• Supply voltage: 2.4 V–3.8 V
• I/O voltage: 1.8 V–3.6 V

• Sleep mode: 7.3 µA (Typical) at 3.3 V VBAT input, wakeup sources from always-on domain, and LFXO_32K running
• Ultra deep sleep mode: 5.0 µA (Typical), with no memory data in retention and wakeup sources from SLP Timer or AON I/Os
• OFF mode: 200 nA (Typical), with system in reset mode

Operating temperature range: –40°C to +85°C

• QFN68: 7.0 x 7.0 x 0.85 mm, 0.35 mm pitch
• QFN56: 7.0 x 7.0 x 0.75 mm, 0.4 mm pitch