Display Refresh Elements

GR5526 provides rich sets of display refresh elements, as listed below.

Table 2 GR5526 display refresh element summary 1

Version	System Main Frequency	X-Flash	External QSPI Frequency	SRAM	QSPI0	QSPI1
Standard version	96 MHz	1 MB	48 MHz	512 KB	NOR Flash (read in XIP mode) NAND Flash (access in register mode) Q-PSRAM (read/write in XIP mode) Display DMA0 (register mode) DMA0/DMA1 (XIP mode) Dynamic adaptive endian Multiple types of static endian 1-wire/2-wire/4-wire mode	NOR Flash (read in XIP mode) NAND Flash (access in register mode) Q-PSRAM (read/write in XIP mode) Display DMA0/DMA1 (register mode) DMA0/DMA1 (XIP mode) Dynamic adaptive endian Multiple types of static endian 1-wire/2-wire/4-wire mode
GPU version

Table 3 GR5526 display refresh element summary 2

Version	QSPI2	DMA	SPIM	DSPI	OSPI DDR PSRAM	GPU	DC
Standard version	NOR Flash (read in XIP mode) NAND Flash (access in register mode) Q-PSRAM (read/write in XIP mode) Display DMA1 (register mode) DMA0/DMA1 (XIP mode) Dynamic adaptive endian Multiple types of static endian 1-wire/2-wire/4-wire mode	2 instances Linked List Scatter Gather Large FIFO depth	48 MHz	48 MHz	N/A	N/A	N/A
GPU version					48 MHz	96 MHz	48 MHz

Major display refresh elements are categorized as follows:

1. Computing power
   1. CPU
   2. GPU (SoC with GPU)
2. Persistent storage of materials/texture data
   1. NOR Flash
   2. NAND Flash
   3. XQSPI Flash (remaining code space, part of which can be used to store data)
3. Computation and buffer space
   1. 512 KB on-chip SRAM
   2. External QSPI PSRAM up to 512 Mbit
   3. Embedded 64 Mbit OSPI DDR PSRAM (SoC with GPU)
4. Data transmission enhancement/Frame rate acceleration
   1. DMA0/DMA1
5. Display interfaces (covering MIPI DBI Type-C interface)
   1. QSPI interface
   2. SPI master interface
   3. Display SPI interface
   4. Display Controller (DC) interface (SoC with GPU)
6. Graphic effect enhancement
   1. GPU (SoC with GPU)
   2. DMA