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Features

  • A Bluetooth Low Energy (Bluetooth LE) 5.1 transceiver integrates Controller and Host layers
    • Supported data rates: 1 Mbps, 2 Mbps, Long Range 500 kbps, Long Range 125 kbps
    • TX power: -20 dBm to +7 dBm
    • -97 dBm sensitivity (in 1 Mbps mode)
    • -93 dBm sensitivity (in 2 Mbps mode)
    • -99.5 dBm sensitivity (in Long Range 500 kbps mode)
    • -103 dBm sensitivity (in Long Range 125 kbps mode)
    • TX current: 3.05 mA @ 0 dBm, 1 Mbps
    • RX current: 3.9 mA @ 1 Mbps
  • ARM® Cortex®-M4F 32-bit micro-processor with floating point support
    • Maximum frequency: 64 MHz
    • Power consumption: 30 µA/MHz
  • Memory
    • 256 KB RAM with retention (four 8 KB RAM blocks and seven 32 KB RAM blocks) for GR5515 series SoCs, and 128 KB RAM with retention (four 8 KB RAM blocks and three 32 KB RAM blocks) for the GR5513 SoC
    • 1 MB Flash for GR5515 series SoCs and 512 KB Flash for the GR5513 SoC (exceptions: GR5515I0ND/GR5515I0NDA requiring external QSPI Flash and GR5515IENDU requiring 512 KB embedded Flash)
  • Power management
    • On-chip DC-DC Converter
    • On-chip I/O LDO to provide I/O voltage and supply external components
    • Supply voltage: 1.7 V to 3.8 V. The supply voltage of GR5515I0ND/GR5515I0NDA (when the external Flash of GR5515I0NDA supplied by high voltage) shall equal the working voltage of external QSPI Flash
    • I/O voltage: 1.8 V to 3.3 V (Typical) (for GR5515I0ND/GR5515I0NDA/GR5515IENDU/GR5513BENDU Flash using high voltage, the VIO_LDO_OUT shall be connected to VBATL in schematic circuit.)
    • OFF mode: 0.15 µA (Typical); nothing is on except VBAT, chip in reset mode
    • Ultra deep sleep mode: 0.65 µA (Typical); I/O LDO off, no memory retention; woken up by AON GPIO or AON Timer
    • Sleep mode: 1.3 µA (Typical) when I/O LDO and BOD/BOD2 turned off, lowest voltage level for memory retention, and 32 KB memory retention; woken up by AON_RTC, AON GPIO, or Bluetooth LE Event
  • Peripherals
    • 2 x QSPI interfaces, up to 32 MHz
    • 2 x SPI interfaces (1 SPI Master Interface with 2 slave CS pins + 1 SPI Slave Interface), up to 32 MHz
    • 2 x I2C interfaces at 100 kHz, 400 kHz, 1 MHz, 2 MHz
    • 2 x I2S interfaces (1 I2S Master Interface + 1 I2S Slave Interface)
    • 2 x UART interfaces, one with DMA channel.
    • 13-bit ADC, up to 1 Msps, 8 channels (5 external test channels and 3 internal signal channels), supporting both single-ended and differential inputs
    • ISO 7816 interface
    • 6-channel PWM
    • Built-in temperature and voltage sensors
    • 4 x Hardware timers
    • 1 x AON hardware timer
    • 2 watchdog timers (one for the system and one is always-on)
    • Calendar timer
    • Wake-up comparator
    • Up to 39 multiplexed GPIO pins
  • Security
    • Complete secure computing engine:
      • AES 128-bit/192-bit/256-bit symmetric encryption (ECB, CBC)
      • Keyed Hash Message Authentication Code (HMAC)
      • PKC
      • TRNG
    • Comprehensive security operation mechanism:
      • Secure boot
      • Encrypted firmware runs directly from Flash
      • eFuse for encrypted key storage
      • Differentiate application data key and firmware key, supporting one data key per device/product
  • Packages
    • QFN56: 7 mm x 7 mm
    • BGA68: 5.3 mm x 5.3 mm
    • BGA55: 3.5 mm x 3.5 mm
    • QFN40: 5 mm x 5 mm
  • Operating temperature range: -40°C to +85°C

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