Hardware Architecture
The GR551x hardware architecture is shown as follows. This section introduces the modules in a GR551x SoC. For more information, see GR551x Datasheet.
- ARM® Cortex®-M4F: GR551x CPU. Bluetooth LE Stack and application code run on the CPU.
- RAM: random access memory that provides memory space for program execution
- ROM: read-only memory, solidifying Bootloader and the software part of Bluetooth LE Stack
- Security Cores: the secure computing engine unit, mainly including TRNG, AES, SHA, and PKC modules, which allows checking encrypted user application firmware. The encrypted firmware is checked through the secure boot process in ROM (In Bluetooth Core Spec, the secure computing unit is an independent module in Communication Core, and is irrelevant to Security Cores).
- Peripherals: GPIO, DMA, I2C, SPI, UART, PWM, Timer, and other hardware
- RF Transceiver: 2.4 GHz RF signal transceiver
- Communication Core: PHY of Bluetooth 5.1 Protocol Stack Controller. It is also the interface between the software protocol stack and 2.4 GHz RF hardware.
- Power Management Unit (PMU): It supplies power for system modules, and sets reasonable parameters for modules, including DC/DC, IO-LDO, Dig-LDO, and RF Subsystem, based on configuration parameters and current running state.
- Flash: Flash memory unit packaged on the SoC. It stores user code and data, and supports the Execute in Place (XIP) Mode for user code.
