RAM Mapping
The RAM of a GR5515 SoC is 256 KB in size with the start address of 0x3000_0000. It consists of 11 RAM Blocks. For the first 4 RAM Blocks, each is 8 KB; for the others, each is 32 KB. Each RAM Block can be powered on/off by software independently.
The GR5515 SoC provides an aliasing memory with the start address of 0x0080_0000 for RAM with the start address of 0x3000_0000, as shown in Figure 4. If the run address of code is within the range of the aliasing memory address, code can run faster in RAM. By default, the aliasing memory is enabled in GR551x SDK.
The 256 KB RAM layout is shown in Figure 8:
Running modes for applications include XIP and Mirror modes. For more information about configurations, see APP_CODE_RUN_ADDR in “Configuring custom_config.h”. RAM layouts of the two modes are different.
| Running Mode | Description |
|---|---|
| XIP Mode |
It refers to Execute in Place Mode. User applications are stored in on-chip Flash, and applications use the same space for running and loading. When the system is powered on, it fetches and executes commands from Flash directly through the Cache Controller. |
| Mirror Mode |
In Mirror Mode, user applications are stored in on-chip Flash, and the running space of applications is defined in RAM. During application boot, applications are loaded into RAM from external Flash after check is completed, and the system jumps to RAM for operation. |
Continuous access to Flash is required in XIP Mode. Therefore, power consumption in this mode is a little higher than that in Mirror Mode.
