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QSPI

QSPI Encounters Abnormalities During Data Transfer at 32 MHz

  • Description

    In both polling and interrupt modes, the QSPI module fails to transfer data at a rate of 32 MHz.

    In DMA mode at 8-bit or 16-bit data width, the QSPI module fails to transfer data at a rate of 32 MHz.

  • Cause

    This abnormality occurs due to relevant IP design limitations. In interrupt or DMA mode, data in QSPI TX FIFO may be consumed to empty without in-time loading of new data when the MCU is inefficient in processing tasks or internal modules within a GR551x system compete for bus resources. In this case, the QSPI controller automatically releases CS signals which lead to timing disorder of QSPI transmission during QSPI TX FIFO reloading. During data reception in DMA mode, when data in QSPI RX FIFO cannot be migrated to SRAM in time due to internal competition for bus resources, RX FIFO overflow occurs, followed by failure to receive data for the QSPI controller.

  • Impact

    A transfer abnormality occurs, and correct data cannot be obtained.

  • Recommended Workaround

    To ensure stable data transfer for QSPI module, choose DMA mode and set a proper transfer rate according to data width. Recommended transfer rates are listed as below:

Table 2 QSPI transfer rates specific to data width
Data Width Transfer Rate QSPI Data Transfer in DMA Mode
8 bits 8 MHz Successful
16 bits 16 MHz Successful
32 bits 32 MHz Successful
Note:

The GR551x QSPI module transfers data in big-endian order while the GR551x system bus adopts little-endian order, resulting in reverse orders of transferred data bytes. Therefore, data processing at the application layer is required.

Mode1 and Mode3 Are Unavailable in Non-Single QSPI Modes

  • Description

    Both Mode1 and Mode3 for the QSPI module are unavailable in non-single (dual-SPI and quad-SPI) modes.

  • Cause

    This abnormality occurs due to relevant IP design limitations.

  • Impact

    A transfer abnormality occurs, and correct data cannot be obtained.

  • Recommended Workaround

    Adopt Mode0 or Mode2 for dual-SPI or quad-SPI data transfer.

    Note:

    Mode 0, Mode1, Mode2, and Mode 3, as four standard clock modes for the QSPI module, are used to configure clock edges and phases for the module.

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