Abnormally High Power Consumption for GR5515I0ND and GR5515I0NDA in Sleep Mode
For GR5515I0ND and GR5515I0NDA that require external Flash, the internal IO LDO of the SoC is used to supply power to external Flash. Relatively small voltage drop (< 100 mA) between VBATL and IO LDO results in electricity leakage which leads to abnormally high power consumption for the SoC.
Electricity leakage is caused due to internal pin status design of the SoC when the voltage drop between VBATL and IO LDO is lower than 100 mA.
The SoC power consumption is abnormally high in sleep mode.
- Recommended Workaround
In application scenarios where the VBATL voltage is close to that provided by the IO LDO (voltage drop < 100 mV), you shall connect VIO_LDO_OUT to VBATL and supply the Flash via VBATL. The following two recommended workarounds are provided to adapt to different application scenarios:
- For GR5515I0ND or GR5515I0NDA that requires 3.3 V external Flash and the VBATL supply voltage is 3.3 V, connect VIO_LDO_OUT to VBATL on the SoC during hardware design. DO NOT use the internal IO LDO of the SoC to supply the external Flash.
- For GR5515I0NDA that requires 1.8 V external Flash and the VBATL supply voltage is 3.3 V, use the internal IO LDO of the SoC to supply the external Flash.
The recommended workaround is available on GR551x SDK V1.6.06 and later versions.