SPI
Transfer Rate of HAL SPI cannot Reach 32 MHz When CS Pins Are Controlled by Hardware
- Description
When the HAL SPI module transfers data in DMA mode, the transfer rate cannot reach 32 MHz if CS pins are controlled by hardware (SPI module).
- Cause
Due to IP design limitations, data in SPI TX FIFO might be depleted when internal modules within a GR551x system compete for bus resources. In this case, the SPI controller automatically releases CS signals which lead to timing disorder of SPI transmission during SPI TX FIFO reloading.
- Impact
A data transfer error occurs.
- Recommended Workaround
Do not control CS pins through hardware. Instead, utilize PIN_MUX registers to configure the CS pins as GPIO pins, and then use software to drive the pins to implement chip select functionality (CS controlled by software). In this case, the SPI module transfers data in DMA mode at 32-bit data width and up to 32 MHz transfer rate.
This workaround has been integrated into GR551x SDK V1.6.06 or later at the driver layer of applications to control CS by software.
