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Features

  • Bluetooth Low Energy 5.3 transceiver integrating Controller and Host layers
    • Supported data rates: 1 Mbps, 2 Mbps, and Long Range (500 kbps, 125 kbps)
    • TX power: -20 dBm to +7 dBm
    • -98 dBm sensitivity (in 1 Mbps mode)
    • -94 dBm sensitivity (in 2 Mbps mode)
    • -101 dBm sensitivity (in Long Range 500 kbps mode)
    • -104 dBm sensitivity (in Long Range 125 kbps mode)
    • TX current: 4.0 mA @ 0 dBm, 1 Mbps
    • RX current: 3.5 mA @ 1 Mbps
    • AoA/AoD, LE Isochronous Channels
  • ARM® Cortex®-M4F 32-bit micro-processor with floating point support
    • Up to 96 MHz clock frequency
    • Built-in Memory Protection Unit (MPU) supporting eight programmable regions
    • Hardware Floating Point Unit (FPU)
    • Built-in Nested Vectored Interrupt Controller (NVIC)
    • Non-maskable Interrupt (NMI) input
    • Serial Wire Debug (SWD) with 16 breakpoints, two watchpoints, and a debug timestamp counter
    • 51 µA/MHz execution from Flash @ 3.3 V, 96 MHz
  • On-chip memory
    • 512 KB data SRAM with retention capabilities
    • 8 KB cache SRAM with retention capabilities
    • Stack ROM (including boot ROM and Bluetooth LE Stack)
    • 1 MB internal QSPI Flash
    • 8 MB internal PSRAM (for GR5526VGBIP and GR5526RGNIP only)
  • Digital peripherals
    • Two general-purpose DMA engines, each with six channels and up to 16 handshaking interfaces
    • USB 2.0 full speed (12 Mbps) controller with on-chip PHY and dedicated DMA controller
    • Internal Octal SPI DDR interfaces to support 8 MB internal PSRAM at up to 48 MHz (for GR5526VGBIP and GR5526RGNIP only)
  • Analog peripherals
    • One 13-bit Sense ADC with a sampling rate of 1 Msps. It supports up to 8 external I/O channels and 3 internal signal channels.
    • Built-in temperature and voltage sensors
    • Low-power comparator, supporting wakeup from deep sleep mode
  • Flexible serial peripherals
    • 6 x UART modules up to 4 Mbps, with all modules supporting flow control and IrDA
    • 6 x I2C modules for peripheral communication, up to 3.4 MHz
    • 1 x 8-bit/16-bit/32-bit SPI master interface and 1 x SPI slave interface for host communication
    • 2 x I2S interfaces (1 I2S master interface and 1 I2S slave interface)
    • PDM interface with hardware sampling rate converter
    • 1 x ISO7816 interface
  • Display/Graphics
    • 2.5D GPU for graphics acceleration (for GR5526VGBIP and GR5526RGNIP only)
    • 1 x Dual-lane SPI (DSPI) interface for display, with Mobile Industry Processor Interface (MIPI) Display Bus Interface (DBI) Type-C support
    • 3 x Quad SPI (QSPI) interfaces, up to 48 MHz; supporting direct access via memory mapping when connecting with external NOR Flash
    • Display Controller (DC) module with MIPI DBI Type-C support and 2D graphics blending integrated (for GR5526VGBIP and GR5526RGNIP only)
  • Security
    • Complete secure computing engine:
      • AES 128-bit/192-bit/256-bit symmetric encryption (ECB, CBC)
      • Hash-based Message Authentication Code (HMAC-SHA256)
      • Public key cryptography (PKC)
      • True random number generator (TRNG)
    • Comprehensive security operation mechanism:
      • Secure boot
      • Encrypted firmware running directly from Flash
      • eFuse for encrypted key storage
      • Differentiate application data key and firmware key, supporting one data key per each device/product
  • I/O Peripherals
    • 50 I/O pins in total
      • 34 general-purpose I/O (GPIO) pins
      • 8 always-on I/O (AON IO) pins, supporting wakeup from deep sleep mode
      • 8 mixed signal I/O (MSIO) pins, configurable to be digital/analog signal interface
  • Timer
    • Two general-purpose, 32-bit timer modules
    • A timer module composed of two programmable 32-bit or 16-bit down counters
    • An internal sleep timer that can be used to wake the device up from deep sleep mode
    • Two PWM modules with edge alignment mode and center alignment mode, each with 3 channels
    • 2 x real-time counters (RTC): 1 x Calendar, 1 x RTC
  • Power management
    • On-chip DC-DC to provide RF Analog voltage and supply core LDO
    • On-chip I/O LDO to provide I/O voltage and supply external components, maximum I/O LDO drive strength: 30 mA
    • Programmable thresholds for brownout detection (BOD)
    • Supply voltage: 2.4 V–4.35 V
    • I/O voltage: 1.8 V–3.6 V
  • Low-power consumption modes
    • Sleep mode: 3.3 µA (Typical) at 3.3 V VBAT input with 128 KB SRAM retention on and LFXO_32K off; woken up by 8 sources of always-on domain
    • Ultra deep sleep mode: 2.4 µA (Typical); internal power (all SRAM included) and LFXO_32K removed from entire chip except always-on domain; woken up by Sleep Timer and AON GPIOs
    • OFF mode: 200 nA (Typical); nothing on except VBAT, and chip in reset mode
  • Packages
    • BGA83: 4.3 x 4.3 x 0.96 (mm), 0.4 mm pitch
    • QFN68: 7.0 x 7.0 x 0.85 (mm), 0.35 mm pitch
  • Operating temperature range: -40°C to +85°C

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