GR5332 RF Transceiver

The system block diagram of a GR5332 RF transceiver is shown as follows:

• On the receiver side:
  1. After the antenna receives an RF signal, the receiver digitizes the signal in a path: Low noise amplifier (LNA) > Mixer > Baseband (BB) amplifier > analog-to-digital converter (ADC).
  2. The digitized signals are sent to the digital frontend (DFE) for demodulation.
  3. The digital frontend provides Automatic Gain Control (AGC) feedback signals to adjust the gain of the LNA and BB amplifier to maximize the signal-to-noise ratio (SNR) at the demodulation.
• On the transmitter side:
  1. The digital signal from the DFE is transmitted to a simplex phase-locked loop (SXPLL) for Gaussian Frequency Shift Keying (GFSK) modulation.
  2. The modulated carrier wave is delivered to a PA (HPA or SPA) through buffer for power amplification, with amplification factor configurable by the digital gain settings.
  3. The modulated carrier wave after power amplification is transmitted to the antenna, which then radiates the amplified carrier wave through electromagnetic waves.
  Note:

  • If an HPA is adopted, the modulated carrier wave needs a single-ended to differential (S2D) conversion before power amplification.
  • The SXPLL reference clock is provided by the external 32 MHz crystal oscillator.
• Power supply
  • The main band gap and HPA in the GR5332 SoC are supplied by VBAT_RF.
  • VDD_RF is the RF input power supply, which powers the VDD_RF, VDD_AMS, and VDD_VCO modules. VDD_RF supplies the RF analog circuits, VDD_AMS supplies the clock module and the receiver baseband module, and VDD_VCO supplies SXPLL.