System Buses

The ARM® Cortex®-M4F processors provide generic bus interfaces based on Advanced Microcontroller Bus Architecture (AMBA). The AMBA specification supports several bus protocols for communication with memories and peripherals.

• I-Code Bus interface: Primarily for program memory; fetches instructions from the ‘Code’ memory space (0x0 to 0x1FFFFFFF).
• D-Code Bus interface: Primarily for program memory; supports data and debug accesses to the ‘Code’ memory space (0x0 to 0x1FFFFFFF).
• System Bus interface: Primarily for RAM and peripherals; accesses to the SRAM and other peripherals of the MCU.

Among them, I-CODE and D-CODE are independent from the system bus, which can realize parallel data access and value acquisition, effectively improving performance. The GR5526 MCU maps the available SRAM onto an address space within the ‘Code’ memory space. This gives the application the opportunity to perform tasks efficiently because the system can quickly finish the task and go to sleep mode.

AMBA supports a variety of bus protocols. For GR5526, the main bus interface uses the AHB Lite protocol. The infrequently accessed peripherals of the GR5526 MCU are located on an AMBA APB bus. There is a bridge which translates the accesses from the System AHB to the APB. Access to these peripherals will inject a single wait-state on the AHB during any access cycle. The system bus diagram of GR5526 is shown in 图 5.

At the same time, the AHB bus has matrix ports, which can support DMA, CPU, and USB to access different memories and peripherals at the same time, beneficial to improve the performance of data access. When multiple masters access the same memory or peripherals, GR5526 uses a round-robin scheduling to configure the priorities of multiple masters. After each response to the master's request, the priority will be determined according to the order of access. This method is more flexible than fixed priority.