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GR5526 Datasheet

版本：

Rev.1.0

V1.3 Rev.1.2 Rev.1.1 Rev.1.0

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文档中心 > GR5526 Datasheet/ Peripherals/ Pin Mux/ Registers Copy URL

Registers

DPAD_MUX_CTRL_00_07

Name: GPIO 00_07 Mux Control Register
Description: This register controls GPIO_0–GPIO_7 mux.
Base Address: 0x4000EE00
Offset: 0x040
Reset Value: 0x77777700

表 138 DPAD_MUX_CTRL_00_07 Register
Bits	Field Name	RW	Reset	Description
31:28	DPAD_MUX_SEL_07	RW	0x7	Value for GPIO_7 mux
27:24	DPAD_MUX_SEL_06	RW	0x7	Value for GPIO_6 mux
23:20	DPAD_MUX_SEL_05	RW	0x7	Value for GPIO_5 mux
19:16	DPAD_MUX_SEL_04	RW	0x7	Value for GPIO_4 mux
15:12	DPAD_MUX_SEL_03	RW	0x7	Value for GPIO_3 mux
11:8	DPAD_MUX_SEL_02	RW	0x7	Value for GPIO_2 mux
7:4	DPAD_MUX_SEL_01	RW	0x0	Value for GPIO_1 mux
3:0	DPAD_MUX_SEL_00	RW	0x0	Value for GPIO_0 mux

DPAD_MUX_CTRL_08_15

Name: GPIO 08_15 Mux Control Register
Description: This register controls GPIO_8–GPIO_15 mux.
Base Address: 0x4000EE00
Offset: 0x044
Reset Value: 0x77777777

表 139 DPAD_MUX_CTRL_08_15 Register
Bits	Field Name	RW	Reset	Description
31:28	DPAD_MUX_SEL_15	RW	0x7	Value for GPIO_15 mux
27:24	DPAD_MUX_SEL_14	RW	0x7	Value for GPIO_14 mux
23:20	DPAD_MUX_SEL_13	RW	0x7	Value for GPIO_13 mux
19:16	DPAD_MUX_SEL_12	RW	0x7	Value for GPIO_12 mux
15:12	DPAD_MUX_SEL_11	RW	0x7	Value for GPIO_11 mux
11:8	DPAD_MUX_SEL_10	RW	0x7	Value for GPIO_10 mux
7:4	DPAD_MUX_SEL_09	RW	0x7	Value for GPIO_9 mux
3:0	DPAD_MUX_SEL_08	RW	0x7	Value for GPIO_8 mux

DPAD_MUX_CTRL_16_23

Name: GPIO 16_23 Mux Control Register
Description: This register controls GPIO_16–GPIO_23 mux.
Base Address: 0x4000EE00
Offset: 0x048
Reset Value: 0x77777777

表 140 DPAD_MUX_CTRL_16_23 Register
Bits	Field Name	RW	Reset	Description
31:28	DPAD_MUX_SEL_23	RW	0x7	Value for GPIO_23 mux
27:24	DPAD_MUX_SEL_22	RW	0x7	Value for GPIO_22 mux
23:20	DPAD_MUX_SEL_21	RW	0x7	Value for GPIO_21 mux
19:16	DPAD_MUX_SEL_20	RW	0x7	Value for GPIO_20 mux
15:12	DPAD_MUX_SEL_19	RW	0x7	Value for GPIO_19 mux
11:8	DPAD_MUX_SEL_18	RW	0x7	Value for GPIO_18 mux
7:4	DPAD_MUX_SEL_17	RW	0x7	Value for GPIO_17 mux
3:0	DPAD_MUX_SEL_16	RW	0x7	Value for GPIO_16 mux

DPAD_MUX_CTRL_24_31

Name: GPIO 24_31 mux control register
Description: This register controls GPIO_24–GPIO_31 mux.
Base Address: 0x4000EE00
Offset: 0x04C
Reset Value: 0x77777777

表 141 DPAD_MUX_CTRL_24_31 Register
Bits	Field Name	RW	Reset	Description
31:28	DPAD_MUX_SEL_31	RW	0x7	Value for GPIO_31 mux
27:24	DPAD_MUX_SEL_30	RW	0x7	Value for GPIO_30 mux
23:20	DPAD_MUX_SEL_29	RW	0x7	Value for GPIO_29 mux
19:16	DPAD_MUX_SEL_28	RW	0x7	Value for GPIO_28 mux
15:12	DPAD_MUX_SEL_27	RW	0x7	Value for GPIO_27 mux
11:8	DPAD_MUX_SEL_26	RW	0x7	Value for GPIO_26 mux
7:4	DPAD_MUX_SEL_25	RW	0x7	Value for GPIO_25 mux
3:0	DPAD_MUX_SEL_24	RW	0x7	Value for GPIO_24 mux

AON_PAD_MUX_CTRL

Name: AON GPIO Pin Mux Control Register
Description: This register controls the AON GPIO pin mux.
Base Address: 0x4000EE00
Offset: 0x050
Reset Value: 0x77777777

表 142 AON_PAD_MUX_CTRL Register
Bits	Field Name	RW	Reset	Description
31	RSVD	R		Reserved bits
30:28	AON_PAD_MUX_SEL_07	RW	0x7	Value for AON_GPIO_7 mux
27	RSVD	R		Reserved bits
26:24	AON_PAD_MUX_SEL_06	RW	0x7	Value for AON_GPIO_6 mux
23	RSVD	R		Reserved bits
22:20	AON_PAD_MUX_SEL_05	RW	0x7	Value for AON_GPIO_5 mux
19	RSVD	R		Reserved bits
18:16	AON_PAD_MUX_SEL_04	RW	0x7	Value for AON_GPIO_4 mux
15	RSVD	R		Reserved bits
14:12	AON_PAD_MUX_SEL_03	RW	0x7	Value for AON_GPIO_3 mux
11	RSVD	R		Reserved bits
10:8	AON_PAD_MUX_SEL_02	RW	0x7	Value for AON_GPIO_2 mux
7	RSVD	R		Reserved bits
6:4	AON_PAD_MUX_SEL_01	RW	0x7	Value for AON_GPIO_1 mux
3:0	RSVD	R		Reserved bits

MSIO_A_PAD_MUX_CTRL

Name: MSIOA Pin Mux Control Register
Description: This register controls the MSIO pin mux.
Base Address: 0x4000EE00
Offset: 0x054
Reset Value: 0x77777777

表 143 MSIO_A_PAD_MUX_CTRL Register
Bits	Field Name	RW	Reset	Description
31	RSVD	R		Reserved bits
30:28	MSIO_A_MUX_SEL_07	RW	0x7	Value for MSIO_7 mux
27	RSVD	R		Reserved bits
26:24	MSIO_A _MUX_SEL_06	RW	0x7	Value for MSIO_6 mux
23	RSVD	R		Reserved bits
22:20	MSIO_A _MUX_SEL_05	RW	0x7	Value for MSIO_5 mux
19	RSVD	R		Reserved bits
18:16	MSIO_A _MUX_SEL_04	RW	0x7	Value for MSIO_4 mux
15	RSVD	R		Reserved bits
14:12	MSIO_A _MUX_SEL_03	RW	0x7	Value for MSIO_3 mux
11	RSVD	R		Reserved bits
10:8	MSIO_A _MUX_SEL_02	RW	0x7	Value for MSIO_2 mux
7	RSVD	R		Reserved bits
6:4	MSIO_A _MUX_SEL_01	RW	0x7	Value for MSIO_1 mux
3	RSVD	R		Reserved bits
2:0	MSIO_A _MUX_SEL_00	RW	0x7	Value for MSIO_0 mux

DPAD_MUX_CTRL_32_33

Name: GPIO 32_33 Mux Control Register
Description: This register controls the GPIO_32– GPIO_33 mux.
Base Address: 0x4000EE00
Offset: 0x058
Reset Value: 0x00000077

表 144 DPAD_MUX_CTRL_32_33 Register
Bits	Field Name	RW	Reset	Description
31:8	RSVD	R		Reserved bits
7:4	DPAD_MUX_SEL_33	RW	0x7	Value for GPIO_33 mux
3:0	DPAD_MUX_SEL_32	RW	0x7	Value for GPIO_32 mux

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