Public Key Cryptography (PKC)

表 690 PKC module standard

Document Code	Name of Standard
FIPS PUB 186-4	Digital Signature Standard (DSS) (Compliant with P-256)
SEC 2	Recommended Elliptic Curve Domain Parameters

The PKC controller module completes the basic underlying modular arithmetic and the FIPS standard 256-point ECC point multiplication in the public key algorithm. GR5526 embeds the PKC module in order to realize hardware acceleration of calculation.

PKC_TOP includes PKC_CORE, PKC_REG, RAND_CLK_GATE, and SP_RAM. PKC_CORE includes PKC_ENGINE and PKC_CTRL sub modules, in which PKC_ENGINE completes the basic underlying modular operations (modular multiplication, modular inversion, modular addition, modular subtraction, modular comparison, modular shift, big integer multiplication, big integer addition, and dummy multiplication) in the public key algorithm.

The ECC point multiplication only supports P-256 curve, such as secp256r1 and secp256k1. The public key algorithm needs a software library which can be open source or user-defined for implementation.

The CTRL register is used to start and reset the PKC module. The STAT register is used to indicate the status of the PKC module. The INT_EN register is used to configure the interrupt mode, and the INT_STAT register is used to indicate the interrupt status.

• Point Multiplication: MCU writes the following parameters to SP_RAM that is a memory area of the PKC module. The parameters include the 256-bit random number k, order n, prime P, base point G, R2mod P, and the initial infinity point Q0. CFG0 to CFG12 registers are used to configure the location pointers. The calculation can be started by using the CTRL register. MCU will read the result from the SP_RAM when the calculation completes. In the interrupt mode, the INT_STAT register can indicate whether the calculation completes.
• Modular Multiplication: MCU writes operand a, operand b, and prime p to SP_RAM. The SW_CFG7 register is used to configure the operand word length. SW_CFG0 and SW_CFG1 registers are used to configure the location pointers. The CFG13 register is used to configure the modular multiplication constant if the lowest 32-bit of prime p is not 0xFFFFFFFF. The calculation can be started by using the CTRL register. MCU will read the result from the SP_RAM when the calculation completes. In the interrupt mode, the INT_STAT register can indicate whether the calculation completes.
• Modular Inversion: MCU writes operand a, modulo p, x1 initial value 1, and x2 initial value 0 to SP_RAM. The SW_CFG7 register is used to configure the operand word length. SW_CFG4 and SW_CFG5 registers are used to configure the location pointers. The SW_CFG6 register is configured to save the intermediate result of modular inversion operation. The calculation can be started by using the CTRL register. MCU will read the modular inversion x1 from the SP_RAM and read the SW_CFG8 register to get the modular inversion k. In the interrupt mode, the INT_STAT register can indicate whether the calculation completes.
• Modular Subtraction and Modular Addition: MCU writes operand a, operand b, and prime p to SP_RAM. The SW_CFG7 register is used to configure the operand word length. SW_CFG2 and SW_CFG3 registers are used to configure the location pointers. The calculation can be started with the CTRL register. MCU will read the result from the SP_RAM when the calculation completes. In the interrupt mode, the INT_STAT register can indicate whether the calculation completes.
• Modular Comparison and Modular Shift: MCU writes operand a and prime p to SP_RAM. The SW_CFG7 register is used to configure the operand word length. SW_CFG0 and SW_CFG1 registers are used to configure the location pointers. The calculation can be started by using the CTRL register. MCU will read the result from the SP_RAM when the calculation completes. In the interrupt mode, the INT_STAT register can indicate whether the calculation completes.
• Big Integer Multiplication: MCU writes operand a and operand b to SP_RAM. The SW_CFG7 register is used to configure the operand word length. The maximum configurable length of the big number multiplication is 1024 bits. SW_CFG10 and SW_CFG11 registers are used to configure the location pointers. The calculation can be started by using the CTRL register. MCU will read the result from the SP_RAM when the calculation completes. In the interrupt mode, the INT_STAT register can indicate whether the calculation completes.
• Big Integer Addition: MCU writes operand a and operand b to SP_RAM. The SW_CFG7 register is used to configure the operand word length. SW_CFG11 and SW_CFG12 registers are used to configure the location pointers. The calculation can be started by using the CTRL register. MCU will read the result from the SP_RAM when the calculation completes. In the interrupt mode, the INT_STAT register can indicate whether the calculation completes.
• Dummy Multiplication: The SW_CFG9 register is used to configure the random seed of dummy multiplication. The dummy multiplication can be started by using the CTRL register. Subsequently, modular addition or big integer addition is performed. The result of the modular addition or the big integer addition can be obtained.
• Random Clock Gating: The SW_CFG13 register is used to configure the random seed of random clock gating. The random clock gating can be enabled by using the CTRL register. Subsequently, PKC operation can be performed.

• Name: PKC Controller Register
• Description: This register acts as a global enable/disable for PKC.
• Base Address: 0x40014000
• Offset: 0x0
• Reset Value: 0x00000000

表 691 PKC Controller Register

Bits	Field Name	RW	Reset	Description
31:9	RSVD	R		Reserved bits
8	RST	RW	0x0	Write 0 and then write 1 to this bit to force the PKC core to reset.
7:5	RSVD	R		Reserved bits
4	SW_CTRL	RW	0x0	Only used in software mode. Value: 0x0: Disable software controller. 0x1: Enable software controller.
3:2	RSVD	R		Reserved bits
1	START	RW	0x0	Only used in hardware mode. After MCU configures all parameters; write 0 and then write 1 to this bit, and the PKC starts to work.
0	EN	RW	0x0	PKC core enable bit Value: 0x0: Disable PKC. 0x1: Enable PKC.

• Name: PKC Configuration 0 Register
• Description: This register acts as a configuration for PKC.
• Base Address: 0x40014000
• Offset: 0x4
• Reset Value: 0x00100000

表 692 PKC Configuration 0 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	R_POINT	RW	0x10	R point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	K_POINT	RW	0x0	K point in sp_ram

• Name: PKC Configuration 1 Register
• Description: This register acts as a configuration for PKC.
• Base Address: 0x40014000
• Offset: 0x8
• Reset Value: 0x00280020

表 693 PKC Configuration 1 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	R2_POINT	RW	0x28	R^2 point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	P_POINT	RW	0x20	P point in sp_ram

• Name: PKC Configuration 2 Register
• Description: This register acts as a configuration for PKC.
• Base Address: 0x40014000
• Offset: 0xC
• Reset Value: 0x00380030

表 694 PKC Configuration 2 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	GY_POINT	RW	0x38	Gy point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	GX_POINT	RW	0x30	Gx point in sp_ram

• Name: PKC Configuration 3 Register
• Description: This register acts as a configuration for PKC.
• Base Address: 0x40014000
• Offset: 0x10
• Reset Value: 0x00480040

表 695 PKC Configuration 3 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	R0X_POINT	RW	0x48	R0x point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	GZ_POINT	RW	0x40	Gz point in sp_ram

• Name: PKC Configuration 4 Register
• Description: This register acts as a configuration for PKC.
• Base Address: 0x40014000
• Offset: 0x14
• Reset Value: 0x00580050

表 696 PKC Configuration 4 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	R0Z_POINT	RW	0x58	R0z point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	R0Y_POINT	RW	0x50	R0y point in sp_ram

• Name: PKC Configuration 5 Register
• Description: This register acts as a configuration for PKC.
• Base Address: 0x40014000
• Offset: 0x18
• Reset Value: 0x00680060

表 697 PKC Configuration 5 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	R1Y_POINT	RW	0x68	R1y point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	R1X_POINT	RW	0x60	R1x point in sp_ram

• Name: PKC Configuration 6 Register
• Description: This register acts as a configuration for PKC.
• Base Address: 0x40014000
• Offset: 0x1C
• Reset Value: 0x00780070

表 698 PKC Configuration 6 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	TEMP1_POINT	RW	0x78	Tmp1 point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	R1Z_POINT	RW	0x70	R1Z point in sp_ram

• Name: PKC Configuration 7 Register
• Description: This register acts as a configuration for PKC.
• Base Address: 0x40014000
• Offset: 0x20
• Reset Value: 0x00880080

表 699 PKC Configuration 7 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	TEMP3_POINT	RW	0x88	TMP3 point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	TEMP2_POINT	RW	0x80	TMP2 point in sp_ram

• Name: PKC Configuration 8 Register
• Description: This register acts as a configuration for PKC.
• Base Address: 0x40014000
• Offset: 0x24
• Reset Value: 0x00980090

表 700 PKC Configuration 8 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	TEMP5_POINT	RW	0x98	TMP5 point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	TEMP4_POINT	RW	0x90	TMP4 point in sp_ram

• Name: PKC Configuration 9 Register
• Description: This register acts as a configuration for PKC.
• Base Address: 0x40014000
• Offset: 0x28
• Reset Value: 0x00A800A0

表 701 PKC Configuration 9 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	CONT1_POINT	RW	0xA8	Constant 1 point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	TEMP6_POINT	RW	0xA0	TMP6 point in sp_ram

• Name: PKC Configuration 10 Register
• Description: This register acts as a configuration for PKC.
• Base Address: 0x40014000
• Offset: 0x2C
• Reset Value: 0x00B800B0

表 702 PKC Configuration 10 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	X2_POINT	RW	0xB8	X2 point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	X1_POINT	RW	0xB0	X1 point in sp_ram

• Name: PKC Configuration 11 Register
• Description: This register acts as a configuration for PKC.
• Base Address: 0x40014000
• Offset: 0x30
• Reset Value: 0x00C800C0

表 703 PKC Configuration 11 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	KT_POINT	RW	0xC8	Software computes 2^256 mod p and writes to sp_ram.
15:9	RSVD	R		Reserved bits
8:0	MIT_POINT	RW	0xC0	Only used in hardware mode. MI point in sp_ram

• Name: PKC Configuration 12 Register
• Description: This register acts as a configuration for PKC.
• Base Address: 0x40014000
• Offset: 0x34
• Reset Value: 0x00D800D0

表 704 PKC Configuration 12 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	B_POINT	RW	0xD8	Curve parameter b in Montgomery field
15:9	RSVD	R		Reserved bits
8:0	A_POINT	RW	0xD0	Curve parameter a in Montgomery field

• Name: PKC Configuration 13 Register
• Description: This register acts as a configuration for PKC.
• Base Address: 0x40014000
• Offset: 0x38
• Reset Value: 0x00000001

表 705 PKC Configuration 13 Register

Bits	Field Name	RW	Reset	Description
31:0	CONSTQ	RW	0x1	Constant used in Montgomery multiplication

• Name: PKC Software Controller Register
• Description: This register acts as a controller for software operation.
• Base Address: 0x40014000
• Offset: 0x40
• Reset Value: 0x00000000

表 706 PKC Software Controller Register

Bits	Field Name	RW	Reset	Description
31:10	RSVD	R		Reserved bits
9	RCG_EN	RW	0x0	Enable random clock gating. Value: 0x0: Disable 0x1: Enable
8	DM_EN	RW	0x0	Enable dummy multiplication. Value: 0x0: Disable 0x1: Enable
7	RSVD	R		Reserved bit
6:4	MODE	RW	0x0	Only used in software mode. Value: 0x0: Montgomery multiplication 0x1: Mod inversion 0x2: Mod addition 0x3: Mod subtraction 0x4: Mod comparison 0x5: Mod shift 0x6: Big integer multiplication 0x7: Bit integer addition
3:1	RSVD	R		Reserved bits
0	START	RW	0x0	Only used in software mode. MCU writes 0 to this bit and then writes 1 to this bit to start the PKC.

• Name: PKC Software Configuration 0 Register
• Description: This register acts as a configuration for PKC in software mode.
• Base Address: 0x40014000
• Offset: 0x44
• Reset Value: 0x00080000

表 707 PKC Software Configuration 0 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	MMB_POINT	RW	0x8	Modular multiplication B point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	MMA_POINT	RW	0x0	Modular multiplication A point in sp_ram

• Name: PKC Software Configuration 1 Register
• Description: This register acts as a configuration for PKC in software mode.
• Base Address: 0x40014000
• Offset: 0x48
• Reset Value: 0x00180010

表 708 PKC Software Configuration 1 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	MMC_POINT	RW	0x18	Modular multiplication C point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	MMP_POINT	RW	0x10	Modular multiplication P point in sp_ram

• Name: PKC Software Configuration 2 Register
• Description: This register acts as a configuration for PKC in software mode.
• Base Address: 0x40014000
• Offset: 0x4C
• Reset Value: 0x00280020

表 709 PKC Software Configuration 2 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	MASB_POINT	RW	0x28	Modular addition/subtraction B point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	MASA_POINT	RW	0x20	Modular addition/subtraction A point in sp_ram

• Name: PKC Software Configuration 3 Register
• Description: This register acts as a configuration for PKC in software mode.
• Base Address: 0x40014000
• Offset: 0x50
• Reset Value: 0x00380030

表 710 PKC Software Configuration 3 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	MASC_POINT	RW	0x38	Modular addition/subtraction C point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	MASP_POINT	RW	0x30	Modular addition/subtraction P point in sp_ram

• Name: PKC Software Configuration 4 Register
• Description: This register acts as a configuration for PKC in software mode.
• Base Address: 0x40014000
• Offset: 0x54
• Reset Value: 0x00480040

表 711 PKC Software Configuration 4 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	MIV_POINT	RW	0x48	Modular inversion V point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	MIU_POINT	RW	0x40	Modular inversion U point in sp_ram

• Name: PKC Software Configuration 5 Register
• Description: This register acts as a configuration for PKC in software mode.
• Base Address: 0x40014000
• Offset: 0x58
• Reset Value: 0x00580050

表 712 PKC Software Configuration 5 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	MIX2_POINT	RW	0x58	Modular inversion X2 point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	MIT_POINT	RW	0x50	Modular inversion X1 point in sp_ram

• Name: PKC Software Configuration 6 Register
• Description: This register acts as a configuration for PKC in software mode.
• Base Address: 0x40014000
• Offset: 0x5C
• Reset Value: 0x00000060

表 713 PKC Software Configuration 6 Register

Bits	Field Name	RW	Reset	Description
31:9	RSVD	R		Reserved bits
8:0	MITP	RW	0x60	Modular inversion TEMP point in sp_ram

• Name: PKC Software Configuration 7 Register
• Description: This register acts as a configuration for PKC in software mode.
• Base Address: 0x40014000
• Offset: 0x60
• Reset Value: 0x00000007

表 714 PKC Software Configuration 7 Register

Bits	Field Name	RW	Reset	Description
31:6	RSVD	R		Reserved bits
5:0	LEN	RW	0x7	Operator word length configuration in software mode: 0x07: 256 bits 0x08: 288 bits … 0x3F: 2048 bits In hardware mode, this register is fixed to 0x07.

• Name: PKC Software Configuration 8 Register
• Description: This register acts as a configuration for PKC in software mode.
• Base Address: 0x40014000
• Offset: 0x64
• Reset Value: 0x00000000

表 715 PKC Software Configuration 8 Register

Bits	Field Name	RW	Reset	Description
31:13	RSVD	R		Reserved bits
12:0	MIK_OUT	R	0x0	K out in modular inversion operation

• Name: PKC Software Configuration 9 Register
• Description: This register acts as a configuration for PKC in software mode.
• Base Address: 0x40014000
• Offset: 0x68
• Reset Value: 0xAABBCCDD

表 716 PKC Software Configuration 9 Register

Bits	Field Name	RW	Reset	Description
31:0	RDMS	RW	0xAABBCCDD	Random dummy multiplication seed

• Name: PKC Software Configuration 10 Register
• Description: This register acts as a configuration for PKC in software mode.
• Base Address: 0x40014000
• Offset: 0x6C
• Reset Value: 0x00780070

表 717 PKC Software Configuration 10 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	BMB_POINT	RW	0x78	Big multiplication B point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	BMA_POINT	RW	0x70	Big multiplication A point in sp_ram

• Name: PKC Software Configuration 11 Register
• Description: This register acts as a configuration for PKC in software mode.
• Base Address: 0x40014000
• Offset: 0x70
• Reset Value: 0x00880080

表 718 PKC Software Configuration 11 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	BAA_POINT	RW	0x88	Big addition A point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	BMC_POINT	RW	0x80	Big multiplication C point in sp_ram

• Name: PKC Software Configuration 12 Register
• Description: This register acts as a configuration for PKC in software mode.
• Base Address: 0x40014000
• Offset: 0x74
• Reset Value: 0x00980090

表 719 PKC Software Configuration 12 Register

Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24:16	BAC_POINT	RW	0x98	Big addition C point in sp_ram
15:9	RSVD	R		Reserved bits
8:0	BAB_POINT	RW	0x90	Big addition B point in sp_ram

• Name: PKC Software Configuration 13 Register
• Description: This register acts as a configuration for PKC in software mode.
• Base Address: 0x40014000
• Offset: 0x78
• Reset Value: 0x11223344

表 720 PKC Software Configuration 13 Register

Bits	Field Name	RW	Reset	Description
31:0	RCG_SEED	RW	0x11223344	Random clock gating seed

• Name: PKC Interrupt Status Register
• Description: This is a read-only register used to indicate the interrupt status of PKC.
• Base Address: 0x40014000
• Offset: 0x80
• Reset Value: 0x00000000

表 721 PKC Interrupt Status Register

Bits	Field Name	RW	Reset	Description
31:3	RSVD	R		Reserved bits
2	BIAO_INT_FLAG	R WC	0x0	PKC big integer add overflow flag. Write 1 to clear.
1	ERR_INT_EN	R WC	0x0	PKC error interrupt flag. Write 1 to clear.
0	CPLT_INT_FLAG	R WC	0x0	PKC complete interrupt flag. Write 1 to clear.

• Name: PKC Interrupt Enable Register
• Description: This register enables or disables all interrupts generated by the PKC.
• Base Address: 0x40014000
• Offset: 0x84
• Reset Value: 0x00000000

表 722 PKC Interrupt Enable Register

Bits	Field Name	RW	Reset	Description
31:3	RSVD	R		Reserved bits
2	BIAO_INT_EN	RW	0x0	PKC big integer add overflow interrupt enable
1	ERR_INT_EN	RW	0x0	PKC error interrupt enable
0	CPLT_INT_EN	RW	0x0	PKC complete interrupt enable

• Name: PKC Status Register
• Description: This is a read-only register used to indicate the status of PKC.
• Base Address: 0x40014000
• Offset: 0x88
• Reset Value: 0x00000000

表 723 PKC Status Register

Bits	Field Name	RW	Reset	Description
31:1	RSVD	R		Reserved bits
0	BUSY	R	0x0	PKC busy status