Registers

Channel_x_Registers

SARx

Name: Source Address for Channel x
Description: The starting source address is programmed by software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the source address of the current AHB transfer.

Note:

You must program the SAR address to be aligned to CTLx.SRC_TR_WIDTH.

Base Address: 0x40013000
Offset: 0x0 + x*0x58
Reset Value: 0x0

表 754 Source Address Register for Channel x
Bits	Field Name	RW	Reset	Description
63:32	RSVD	R		Reserved field
31:0	SRC_ADDR	RW	0x0	Current Source Address of DMA transfer. Updated after each source transfer. The SRC_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every source transfer through the block transfer. Volatile: true

DARx

Name: Destination Address Register for Channel x
Description: The starting destination address is programmed by software before the DMA channel is enabled, or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress, this register is updated to reflect the destination address of the current AHB transfer.

Note:

You must program the DAR to be aligned to CTLx.DST_TR_WIDTH.

Base Address: 0x40013000
Offset: 0x8 + x*0x58
Reset Value: 0x0

表 755 Destination Address Register for Channel x
Bits	Field Name	RW	Reset	Description
63:32	RSVD	R		Reserved field
31:0	DEST_ADDR	RW	0x0	Current Destination address of DMA transfer. Updated after each destination transfer. The DEST_ADDR_INC field in the CTRL_CHx register determines whether the address increments, decrements, or is left unchanged on every destination transfer throughout the block transfer. Volatile: true

LLPx

Name: Linked List Pointer Register for Channel x
Description: The LLP register has two functions:
- The logical result of the equation LLP.LOC !=0 is used to set up the type of DMA transfer: single or multi-block. If LLP.LOC is set to 0x0, transfers using linked lists are not enabled. This register must be programmed prior to enabling the channel in order to set up the transfer type.
- LLP.LOC != 0 contains the pointer to the next LLI for block chaining using linked lists. The LLPx register can also point to the address where write back of the control and source/destination status information occurs after block completion.
Base Address: 0x40013000
Offset: 0x10 + x*0x58
Reset Value: 0x0

表 756 Linked List Pointer Register for Channel x
Bits	Field Name	RW	Reset	Description
63:32	RSVD	R		Reserved field
31:2	LOC	RW	0x0	Starting Address In Memory of next LLI if block chaining is enabled. Note that the two LSBs of the starting address are not stored because the address is assumed to be aligned to a 32-bit boundary. LLI accesses are always 32-bit accesses (Hsize = 2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. Volatile: true
1:0	RSVD	R		Reserved field

CTLx

Name: Control Register for Channel x
Description: This register contains fields that control the DMA transfer. The CTLx register is part of the block descriptor (linked list item - LLI) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block chaining is enabled. If status write-back is enabled, the upper word of the control register, CTLx[63:32], is written to the control register location of the LLI in system memory at the end of the block transfer.

Note:

You need to program this register prior to enabling the channel.

Base Address: 0x40013000
Offset: 0x18 + x*0x58
Reset Value: 0x0000000200304801

表 757 Control Register for Channel x
Bits	Field Name	RW	Reset	Description
63:45	RSVD	R	0x0	Reserved field Volatile: true
44	DONE	RW	0x0	Done bit. If status write-back is enabled, the upper word of the control register, CTRL_CHx[63:32], is written to the control register location of the LLI in system memory at the end of the block transfer with the done bit set. Software can poll the LLI CTRL_CHx.DONE bit to see when a block transfer completes. The LLI CTRL_CHx.DONE bit should be cleared when the linked lists are set up in memory prior to enabling the channel. LLI accesses are always 32-bit accesses (Hsize = 2) aligned to 32-bit boundaries and cannot be changed or programmed to anything other than 32-bit. Volatile: true
43:32	BLOCK_XFE_SIZE	RW	0x2	Block Transfer Size. When the DMA is the flow controller, users write this field before the channel is enabled in order to indicate the block size. The number programmed into BLOCK_XFE_SIZE indicates the total number of single transactions to perform for every block transfer; a single transaction is mapped to a single AMBA beat. Width: The width of single transaction is determined by CTRL_CHx.SRC_XFE_WIDTH. Once the transfer starts, the read-back value is the total number of data items already read from the source peripheral, regardless of what the flow controller is. When the source or destination peripheral is assigned as the flow controller, the maximum block size that can be read back saturates at 0xFFF, but the actual block size can be greater. Volatile: true
31:29	Rsvd_1_CTRL	R	0x0	Reserved field Volatile: true
28	LLP_SRC_EN	RW	0x0	Block chaining is enabled on the source side only if the LLP_SRC_EN field is high and LLPx.LOC is non-zero. Value: 0x0 (LLP_SRC_DISABLE): Block chaining using linked list is disabled on the source side. 0x1 (LLP_SRC_ENABLE): Block chaining using linked list is enabled on the source side. 0x0 (DISABLED): DONE bit is deasserted at the end of block transfer. 0x1 (ENABLED): SET the DONE bit at the end of block transfer. Volatile: true
27	LLP_DST_EN	RW	0x0	Block chaining is enabled on the destination side only if LLP_DST_EN field is high and LLPx.LOC is non-zero. Value: 0x0 (LLP_DST_DISABLE): Block chaining using linked list is disabled on the destination side. 0x1 (LLP_DST_ENABLE): Block chaining using linked list is enabled on the destination side. Volatile: true
26:23	Rsvd	R	0x0	Reserved field Volatile: true
22:20	XFE_TYPE_FC	RW	0x3	Transfer Type and Flow Control. Flow control can be assigned to the DMA, the source peripheral, or the destination peripheral. Value: 0x0: Transfer type is memory to memory, and flow controller is DMA. 0x1: Transfer type is memory to peripheral, and flow controller is DMA. 0x2: Transfer type is Peripheral to memory, and flow controller is DMA. 0x3: Transfer type is peripheral to peripheral, and flow controller is DMA. Volatile: true
19	Rsvd_CTRL	R	0x0	Reserved field Volatile: true
18	DST_SCATTER_EN	RW	0x0	Destination scatter enable. Scatter on the destination side is applicable only when the CTLx.DINC bit indicates an incrementing or decrementing address control. Value: 0x0 (DST_SCATTER_DISABLE): Destination scatter is disabled. 0x1 (DST_SCATTER_ENABLE): Destination scatter is enabled. Volatile: true
17	SRC_GATHER_EN	RW	0x0	Source gather enable. Gather on the source side is applicable only when the CTLx.DINC bit indicates an incrementing or decrementing address control. Value: 0x0 (SRC_GATHER_DISABLE): Source gather is disabled. 0x1 (SRC_GATHER_ENABLE): Source gather is enabled. Volatile: true
16:14	SRC_MSIZE	RW	0x1	Source burst transaction length. Number of data items, each of width CTRL_CHx.SRC_XFE_WIDTH, to be read from the source every time a burst transferred request is made from either the corresponding hardware or software handshaking interface. Note: This value is not related to the AHB bus master HBURST bus. Value: 0x0: Number of data items to be transferred is 1. 0x1: Number of data items to be transferred is 4. 0x2: Number of data items to be transferred is 8. Volatile: true
13:11	DEST_MSIZE	RW	0x1	Destination burst transaction length. Number of data items, each of width CTRL_CHx.DEST_XFE_WIDTH, to be written to the destination every time a destination burst transaction request is made from either the corresponding hardware or software handshaking interface. Note: This value is not related to the AHB bus master HBURST bus. Value: 0x0: Number of data items to be transferred is 1. 0x1: Number of data items to be transferred is 4. 0x2: Number of data items to be transferred is 8. Volatile: true
10:9	SRC_ADDR_INC	RW	0x0	Source address increment. Indicates whether to increment or decrement the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, set this field to "No change". Value: 0x0: Increments the source address. 0x1: Decrements the source address. 0x2/0x3: No change in the source address Volatile: true
8:7	DEST_ADDR_INC	RW	0x0	Destination address increment. Indicates whether to increment or decrement the destination address on every destination transfer. If your device is writing data to a destination peripheral FIFO with a fixed address, set this field to "No Change". Value: 0x0: Increments the destination address. 0x1: Decrements the destination address. 0x2/0x3: No change in the destination address Volatile: true
6:4	SRC_XFE_WIDTH	RW	0x0	Source Transfer Width. Mapped to AHB bus Hsize. For a non-memory peripheral, typically the peripheral (source) FIFO width. Value: 0x0: Source transfer width is 8 bits. 0x1: Source transfer width is 16 bits. 0x2: Source transfer width is 32 bits. Volatile: true
3:1	DEST_XFE_WIDTH	RW	0x0	Destination Transfer Width. Mapped to AHB bus Hsize. For a non-memory peripheral, typically the peripheral (destination) FIFO width. Value: • 0x0: Destination transfer width is 8 bits. • 0x1: Destination transfer width is 16 bits. • 0x2: Destination transfer width is 32 bits. Volatile: true
0	INT_EN	RW	0x1	Interrupt Enable Bit. If set, all interrupt-generating sources are enabled. Functions as a global mask bit for all interrupts for the channel; raw interrupt registers still assert if CTRL_CHx.INT_EN = 0. Value: 0x0: Interrupt is disabled. 0x1: Interrupt is enabled. Volatile: true

SSTATx

Name: Source Status Register for Channel x
Description: After each block transfer completes, hardware can retrieve the source status information from the address pointed to by the contents of the SSTATARx register. This status information is then stored in the SSTATx register and written out to the SSTATx register location of the LLI before the start of the next block. For conditions under which the source status information is fetched, it can be varied on a block-by-block basis within a DMA transfer when block chaining is enabled. If status write-back is enabled, the upper word of the control register, CTLx[63:32], is written to the control register location of the LLI in system memory at the end of the block transfer.

Note:

This register is a temporary placeholder for the source status information on its way to the SSTATx register location of the LLI. The source status information should be retrieved by software from the SSTATx register location of the LLI, and not by a read of this register over the DMA controller slave interface.

Base Address: 0x40013000
Offset: 0x20 + x*0x58
Reset Value: 0x0

表 758 Source Status Register for Channel x
Bits	Field Name	RW	Reset	Description
63:32	RSVD	R		Reserved field
31:0	SSTAT	RW	0x0	Source status information retrieved by hardware from the address pointed to by the contents of the STATARx register Volatile: true

DSTATx

Name: Destination Status Register for Channel x
Description: After each block transfer completes, hardware can retrieve the destination status information from the address pointed to by the contents of the DSTATARx register. This status information is then stored in the DSTATx register and written out to the DSTATx register location of the LLI before the start of the next block.

Note:

This register is a temporary placeholder for the destination status information on its way to the DSTATx register location of the LLI. The destination status information should be retrieved by software from the DSTATx register location of the LLI, and not by a read of this register over the DMAC controller slave interface.

Base Address: 0x40013000
Offset: 0x28 + x*0x58
Reset Value: 0x0

表 759 Destination Status Register for Channel x
Bits	Field Name	RW	Reset	Description
63:32	RSVD	R		Reserved field
31:0	DSTAT	RW	0x0	Destination status information retrieved by hardware from the address pointed to by the contents of the DSTATARx register Volatile: true

SSTATARx

Name: Source Status Address Register for Channel x
Description: After completion of each block transfer, hardware can retrieve the source status information from the user-defined address to which the contents of the SSTATARx register point. Users can select any location in system memory that would provide a 32-bit value to indicate the status of the source transfer.
Base Address: 0x40013000
Offset: 0x30 + x*0x58
Reset Value: 0x0

表 760 Source Status Address Register for Channel x
Bits	Field Name	RW	Reset	Description
63:32	RSVD	R		Reserved field
31:0	SSTATAR	RW	0x0	Pointer from where hardware can fetch the source status information which is registered in the SSTATx register and written out to the SSTATx register location of the LLI before the start of the next block.

DSTATARx

Name: Destination Status Address Register for Channel x
Description: After completion of each block transfer, hardware can retrieve the destination status information from the user-defined address to which the contents of the DSTATARx register point. Users can select any location in system memory that would provide a 32-bit value to indicate the status of the destination transfer.
Base Address: 0x40013000
Offset: 0x38 + x*0x58
Reset Value: 0x0

表 761 Destination Status Address Register for Channel x
Bits	Field Name	RW	Reset	Description
63:32	RSVD	R		Reserved field
31:0	DSTATAR	RW	0x0	Pointer from where hardware can fetch the destination status information which is registered in the DSTATx register and written out to the DSTATx register location of the LLI before the start of the next block.

CFGx

Name: Configuration Register for Channel x
Description: This register contains fields that configure the DMA transfer. The channel configuration register remains fixed for all blocks of a multi-block transfer.

Note:

You need to program this register prior to enabling the channel.

Base Address: 0x40013000
Offset: 0x40 + x*0x58
Reset Value: 0x0000000400000e00 + (x*0x20)

表 762 Configuration Register for Channel x
Bits	Field Name	RW	Reset	Description
63:47	RSVD	R		Reserved field
46:43	DEST_PER	RW	0x0	Destination hardware interface. Assigns a hardware handshaking interface to the destination of channel x if the CFG_CHx.HSG_SEL_DEST field is 0; otherwise, this field is ignored. The channel can communicate with the destination peripheral connected to that interface through the assigned hardware handshaking interface. Note: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
42:39	SRC_PER	RW	0x0	Source hardware interface. Assigns a hardware handshaking interface to the source of channel x if the CFG_CHx.HSG_SEL_SRC field is 0; otherwise, this field is ignored. The channel can then communicate with the source peripheral connected to that interface through the assigned hardware handshaking interface. Note: For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking interface.
38	SS_UPD_EN	RW	0x0	Source status update enable. Source status information is fetched only from the location pointed to by the SSTATARx register, stored in the SSTATx register and written out to the SSTATx location of the LLI, if SS_UPD_EN is high. Value: 0x0 (DISABLED): Source status update is disabled. 0x1 (ENABLED): Source status update is enabled.
37	DS_UPD_EN	RW	0x0	Destination status update enable. Destination status information is fetched only from the location pointed to by the DSTATARx register, stored in the DSTATx register and written out to the DSTATx location of the LLI, if DS_UPD_EN is high. Value: 0x0 (DISABLED): Destination status update is disabled. 0x1 (ENABLED): Destination status update is enabled.
36:34	PROT_CTRL	RW	0x0	Protection control bits used to drive the AHB HPROT[3:1] bus. The AMBA specification recommends that the default of HPROT indicate a non-cached, non-buffered, and privileged data access. The reset value is used to indicate such an access. HPROT[0] is tied high because all transfers are data accesses, as there are no opcode fetches. There is a one-to-one mapping of these register bits to the HPROT[3:1] master interface signals. Mapping of HPROT bus is as follows: 0x1 to HPROT[0] CFGx.PROT_CTRL[1] to HPROT[1] CFGx.PROT_CTRL[2] to HPROT[2] CFGx.PROT_CTRL[3] to HPROT[3]
33	FIFO_MODE	RW	0x0	FIFO mode select. Determines how much space or data needs to be available in the FIFO before a burst transaction request is serviced. Value: 0x0: Space/Data available for a single AHB transfer of the specified transfer width 0x1: Data available is greater than or equal to half the FIFO depth for destination transfers, and space available is greater than half the FIFO depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer.
32	FLOW_CTRL_MODE	RW	0x0	Flow control mode. Determines when source transaction requests are serviced when the destination peripheral is the flow controller. Value: 0x0: Source transaction requests are serviced when they occur. Data pre-fetching is enabled. 0x1: Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled.
31	RELOAD_DEST	RW	0x0	Automatic destination reload. The DARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. Value: 0x0: Destination reload disabled 0x1: Destination reload enabled
30	RELOAD_SRC	RW	0x0	Automatic source reload. The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A new block transfer is then initiated. Value: 0x0: Source reload disabled 0x1: Source reload enabled
29:20	Rsvd_CFG	R	0x0	Reserved field
19	SRC_HSG_POL	RW	0x0	Source handshaking interface polarity. Value: 0x0: Source handshaking interface polarity is active high. 0x1: Source handshaking interface polarity is active low.
18	DEST_HSG_POL	RW	0x0	Destination handshaking interface polarity. Value: 0x0: Destination handshaking interface polarity is active high. 0x1: Destination handshaking interface polarity is active low.
17:12	Rsvd_CFG	R	0x0	Reserved field
11	HSG_SEL_SRC	RW	0x0	Selects software or hardware handshaking interface for source. This register selects which of the handshaking interfaces - hardware or software - is active for source requests on this channel. If the source peripheral is memory, this bit is ignored. Value: 0x0: Hardware handshaking interface. Software initiated transaction requests are ignored. 0x1: Software handshaking interface. Hardware initiated transaction requests are ignored.
10	HSG_SEL_DEST	RW	0x0	Selects a software or hardware handshaking interface for destination. This register selects which of the handshaking interfaces - hardware or software - is active for destination requests on this channel. If the destination peripheral is memory, this bit is ignored. Value: 0x0: Hardware handshaking interface. Software initiated transaction requests are ignored. 0x1: Software handshaking interface. Hardware initiated transaction requests are ignored.
9	FIFO_EMPTY	R	0x0	Channel FIFO status. Indicates if there is data left in the channel FIFO. It can be used in conjunction with CFGx to cleanly disable a channel. Value: 0x0: Channel FIFO is not empty. 0x1: Channel FIFO is empty.
8	CH_SUSP	RW	0x0	Channel suspend. Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction will complete. It can also be used in conjunction with CFGx to cleanly disable a channel without losing any data. Value: 0x0: DMA transfer from the source is not suspended. 0x1: Suspend DMA transfer from the source.
7:5	CH_PRIOR	RW		Channel priority. A priority of 7 is the highest priority and 0 is the lowest. This field must be programmed within the range of 0 to 3. A programmed value beyond this range will cause erroneous behavior. Value: 0x0: Channel priority is 0. 0x1: Channel priority is 1. 0x2: Channel priority is 2. 0x3: Channel priority is 3.
4:0	RSVD	R		Reserved field

SGRx

Name: Source Gather Register for Channel x
Description: The Source Gather Register contains two fields.
- Source gather count field (SGRx.SGC): Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH between successive gather intervals. This is defined as a gather boundary.
- Source gather interval field (SGRx.SGI): Specifies the source address increment/decrement in multiples of CTLx.SRC_TR_WIDTH on a gather boundary when gather mode is enabled for the source transfer.
Base Address: 0x40013000
Offset: 0x48 + x*0x58
Reset Value: 0x0

表 763 Source Gather Register for Channel x
Bits	Field Name	RW	Reset	Description
63:32	RSVD	R		Reserved field
31:20	SGC	RW	0x0	Source gather count.
19:0	SGI	RW	0x0	Source gather interval.

DSRx

Name: Destination Scatter Register for Channel x
Description: The Destination Status Register contains two fields.
- Destination scatter count field (DSRx.DSC): Specifies the number of contiguous destination transfers of CTLx.DST_TR_WIDTH between successive scatter boundaries.
- Destination scatter interval field (DSRx.DSI): Specifies the destination address increment/decrement in multiples of CTLx.DST_TR_WIDTH on a scatter boundary when scatter mode is enabled for the destination transfer.
Base Address: 0x40013000
Offset: 0x50 + x*0x58
Reset Value: 0x0

表 764 Destination Scatter Register for Channel x
Bits	Field Name	RW	Reset	Description
63:32	RSVD	R		Reserved field
31:20	DSC	RW	0x0	Destination scatter count.
19:0	DSI	RW	0x0	Destination scatter interval.

Interrupt_Registers

INT_RSTAT_TC

Name: Raw Status for Transfer Complete Interrupt
Description: Interrupt events are stored in this Raw Interrupt Status Register before masking. This register has a bit allocated to each channel; for example, INT_RSTAT_TC[2] is the Channel 2 raw transfer complete interrupt. Each bit in this register is cleared by writing a 1 to the corresponding location in the INT_CLR_TC register.

Note:

Write access is available to this register or software for testing purposes only. Under normal operation, writes to this register are not recommended.

Base Address: 0x40013000
Offset: 0x2c0
Reset Value: 0x0

表 765 Raw Status for Transfer Complete Interrupt
Bits	Field Name	RW	Reset	Description
63:8	Rsvd_INT_RSTAT_TC	R	0x0	Reserved field
7:0	RAW	RW	0x0	Raw status for transfer complete interrupt Value: 0x0: Inactive raw interrupt status 0x1: Active raw interrupt status

INT_RSTAT_BTC

Name: Raw Status for Block Transfer Complete Interrupt
Description: Interrupt events are stored in this Raw Interrupt Status Register before masking. This register has a bit allocated to each channel; for example, INT_RSTAT_BTC[2] is the Channel 2 raw block complete interrupt. Each bit in this register is cleared by writing a 1 to the corresponding location in the CLR_BLK register.

Note:

Write access is available to this register or software for testing purposes only. Under normal operation, writes to this register are not recommended.

Base Address: 0x40013000
Offset: 0x2c8
Reset Value: 0x0

表 766 Raw Status for Block Transfer Complete Interrupt
Bits	Field Name	RW	Reset	Description
63:8	RSVD_INT_RSTAT_BTC	R	0x0	Reserved field
7:0	RAW	RW	0x0	Raw Status for Block Transfer Complete Interrupt Value: 0x0: Inactive raw interrupt status 0x1: Active raw interrupt status

INT_RSTAT_STC

Name: Raw Status for Source Transaction Complete Interrupt
Description: Interrupt events are stored in this Raw Interrupt Status Register before masking. This register has a bit allocated to each channel; for example, INT_RSTAT_STC[2] is the Channel 2 raw source transaction complete interrupt. Each bit in this register is cleared by writing a 1 to the corresponding location in the INT_CLR_STC register.

Note:

Write access is available to this register or software testing purposes only. Under normal operation, writes to this register are not recommended.

Base Address: 0x40013000
Offset: 0x2D0
Reset Value: 0x0

表 767 Raw Status for Source Transaction Complete Interrupt
Bits	Field Name	RW	Reset	Description
63:8	RSVD_INT_RSTAT_STC	R	0x0	Reserved field
7:0	RAW	RW	0x0	Raw status for source transaction complete interrupt Value: 0x0: Inactive raw interrupt status 0x1: Active raw interrupt status

INT_RSTAT_DTC

Name: Raw Status for Destination Transaction Complete Interrupt
Description: Interrupt events are stored in this Raw Interrupt Status register before masking. This register has a bit allocated to each channel; for example, INT_RSTAT_DTC[2] is the Channel 2 raw destination transaction complete interrupt. Each bit in this register is cleared by writing a 1 to the corresponding location in the INT_CLR_DTC register.

Note:

Write access is available to this register or software testing purposes only. Under normal operation, writes to this register are not recommended.

Base Address: 0x40013000
Offset: 0x2d8
Reset Value: 0x0

表 768 Raw Status for Destination Transaction Complete Interrupt
Bits	Field Name	RW	Reset	Description
63:8	RSVD_INT_RSTAT_DTC	R	0x0	Reserved field
7:0	RAW	RW	0x0	Raw status for destination transaction complete interrupt Value: 0x0: Inactive raw interrupt status 0x1: Active raw interrupt status

INT_RSTAT_ERR

Name: Raw Status for Error Interrupt
Description: Interrupt events are stored in this Raw Interrupt Status Register before masking. This register has a bit allocated to each channel; for example, INT_RSTAT_ERR[2] is the Channel 2 raw error interrupt. Each bit in this register is cleared by writing a 1 to the corresponding location in the INT_CLR_ERR register.

Note:

Write access is available to this register or software testing purposes only. Under normal operation, writes to this register are not recommended.

Base Address: 0x40013000
Offset: 0x2E0
Reset Value: 0x0

表 769 Raw Status for Error Interrupt
Bits	Field Name	RW	Reset	Description
63:8	RSVD_INT_RSTAT_ERR	R	0x0	Reserved field
7:0	RAW	RW	0x0	Raw Status for Error Interrupt Value: 0x0: Inactive raw interrupt status 0x1: Active raw interrupt status

INT_STAT_TC

Name: Status for Transfer Complete Interrupt
Description: Channel DMA transfer complete interrupt events from all channels are stored in this interrupt status register after masking. This register has a bit allocated to each channel; for example, INT_STAT_TC [2] is the Channel 2 source DMA transfer complete interrupt. The contents of this register are used to generate the interrupt signals (int or int_n bus, depending on interrupt polarity) leaving the DMA.
Base Address: 0x40013000
Offset: 0x2E8
Reset Value: 0x0

表 770 Status for Transfer Complete Interrupt
Bits	Field Name	RW	Reset	Description
63:8	RSVD_INT_STAT_TC	R	0x0	Reserved field
7:0	STAT	R	0x0	Status for transfer complete interrupt Value: 0x0: Inactive interrupt status 0x1: Active interrupt status

INT_STAT_BTC

Name: Status for Block Transfer Complete Interrupt
Description: Channel block complete interrupt events from all channels are stored in this interrupt status register after masking. This register has a bit allocated to each channel; for example, INT_STAT_BTC[2] is the Channel 2 block complete interrupt. The contents of this register are used to generate the interrupt signals (int or int_n bus, depending on interrupt polarity) leaving the DMA.
Base Address: 0x40013000
Offset: 0x2F0
Reset Value: 0x0

表 771 Status for Block Transfer Complete Interrupt
Bits	Field Name	RW	Reset	Description
63:8	RSVD_INT_STAT_BTC	R	0x0	Reserved field
7:0	STAT	R	0x0	Status for block transfer complete interrupt Value: 0x0: Inactive interrupt status 0x1: Active interrupt status

INT_STAT_STC

Name: Status for Source Transaction Complete Interrupt
Description: Channel source transaction complete interrupt events from all channels are stored in this interrupt status register after masking. This register has a bit allocated to each channel; for example, INT_STAT_STC[2] is the Channel 2 source transaction complete interrupt. The contents of this register are used to generate the interrupt signals (int or int_n bus, depending on interrupt polarity) leaving the DMA.
Base Address: 0x40013000
Offset: 0x2F8
Reset Value: 0x0

表 772 Status for Source Transaction Complete Interrupt
Bits	Field Name	RW	Reset	Description
63:8	RSVD_INT_STAT_STC	R	0x0	Reserved field
7:0	STAT	R	0x0	Status for source transaction complete interrupt Value: 0x0: Inactive interrupt status 0x1: Active interrupt status

INT_STAT_DTC

Name: Status for Destination Transaction Complete Interrupt
Description: Channel destination transaction complete interrupt events from all channels are stored in this interrupt status register after masking. This register has a bit allocated to each channel; for example, INT_STAT_DTC[2] is the Channel 2 status destination transaction complete interrupt. The contents of this register are used to generate the interrupt signals (int or int_n bus, depending on interrupt polarity) leaving the DMA.
Base Address: 0x40013000
Offset: 0x300
Reset Value: 0x0

表 773 Status for Destination Transaction Complete Interrupt
Bits	Field Name	RW	Reset	Description
63:8	RSVD_INT_STAT_DTC	R	0x0	Reserved field
7:0	STAT	R	0x0	Status for destination transaction complete interrupt Value: 0x0: Inactive interrupt status 0x1: Active interrupt status

INT_STAT_ERR

Name: Status for Error Interrupt
Description: Channel error interrupt events from all channels are stored in this interrupt status register after masking. This register has a bit allocated to each channel; for example, INT_STAT_ERR[2] is the Channel 2 status error interrupt. The contents of this register are used to generate the interrupt signals (int or int_n bus, depending on interrupt polarity) leaving the DMA.
Base Address: 0x40013000
Offset: 0x308
Reset Value: 0x0

表 774 Status for Error Interrupt
Bits	Field Name	RW	Reset	Description
63:8	RSVD_INT_STAT_ERR	R	0x0	Reserved field
7:0	STAT	R	0x0	Status for error interrupt Value: 0x0: Inactive interrupt status 0x1: Active interrupt status

INT_MASK_TC

Name: MASK for Transfer Complete Interrupt
Description: The contents of the raw status register INT_RSTAT_TC are masked with the contents of the mask register INT_MASK_TC. This register has a bit allocated to each channel; for example, INT_MASK_TC[2] is the mask bit for the Channel 2 transfer complete interrupt. A channel INT_MASK bit will be written only if the corresponding mask write enable bit in the INT_MASK_WE field is asserted on the same AHB write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, writing hex 01x1 to the INT_MASK_TC register writes a 1 into INT_MASK_TC[0], while INT_MASK_TC[7:1] remains unchanged. Writing hex 00xx leaves INT_MASK_TC[7:0] unchanged. Writing a 1 to any bit in this register unmasks the corresponding interrupt, thus allowing the DMA to set the appropriate bit in the status registers and int_port signals.
Base Address: 0x40013000
Offset: 0x310
Reset Value: 0x0

表 775 MASK for Transfer Complete Interrupt
Bits	Field Name	RW	Reset	Description
63:16	RSVD_INT_MASK_TC	R	0x0	Reserved field
15:8	INT_MASK_WE	W	0x0	Interrupt Mask Write Enable Value: 0x0: Interrupt mask write disabled 0x1: Interrupt mask write enabled
7:0	INT_MASK	RW	0x0	Mask for Transfer Complete Interrupt Value: 0x0: Mask the interrupts. 0x1: Unmask the interrupts.

INT_MASK_BTC

Name: Mask for Block Transfer Complete Interrupt
Description: The contents of the raw status register INT_RSTAT_BTC are masked with the contents of the mask register INT_MASK_BTC. This register has a bit allocated to each channel; for example, INT_MASK_BTC[2] is the mask bit for the Channel 2 block complete interrupt. A channel INT_MASK bit will be written only if the corresponding mask write enable bit in the INT_MASK_WE field is asserted on the same AHB write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, writing hex 01x1 to the INT_MASK_BTC register writes a 1 into INT_MASK_BTC[0], while INT_MASK_BTC[7:1] remains unchanged. Writing hex 00xx leaves INT_MASK_BTC[7:0] unchanged. Writing a 1 to any bit in this register unmasks the corresponding interrupt, thus allowing the DMA to set the appropriate bit in the status registers and int_port signals.
Base Address: 0x40013000
Offset: 0x318
Reset Value: 0x0

表 776 Mask for Block Transfer Complete Interrupt
Bits	Field Name	RW	Reset	Description
63:16	RSVD_INT_MASK_BTC	R	0x0	Reserved field
15:8	INT_MASK_WE	W	0x0	Interrupt Mask Write Enable Value: 0x0: Interrupt mask write disabled 0x1: Interrupt mask write enabled
7:0	INT_MASK	RW	0x0	Mask for Block Transfer Complete Interrupt Value: 0x0: Mask the interrupts. 0x1: Unmask the interrupts.

INT_MASK_STC

Name: MASK for Source Transaction Complete Interrupt
Description: The contents of the raw status register INT_RSTAT_STC are masked with the contents of the mask register INT_MASK_STC. This register has a bit allocated to each channel; for example, INT_MASK_STC[2] is the mask bit for the Channel 2 source transaction complete interrupt. When the source peripheral of DMA channel i is memory, then the source transaction complete interrupt, INT_MASK_STC[i], must be masked to prevent an erroneous triggering of an interrupt on the int_combined signal. A channel INT_MASK bit will be written only if the corresponding mask write enable bit in the INT_MASK_WE field is asserted on the same AHB write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, writing hex 01x1 to the INT_MASK_STC register writes a 1 into INT_MASK_STC[0], while INT_MASK_STC[7:1] remains unchanged. Writing hex 00xx leaves INT_MASK_STC[7:0] unchanged. Writing a 1 to any bit in this register unmasks the corresponding interrupt, thus allowing the DMA to set the appropriate bit in the status registers and int_port signals.
Base Address: 0x40013000
Offset: 0x320
Reset Value: 0x0

表 777 MASK for Source Transaction Complete Interrupt
Bits	Field Name	RW	Reset	Description
63:16	RSVD_INT_MASK_STC	R	0x0	Reserved field
15:8	INT_MASK_WE	W	0x0	Interrupt Mask Write Enable Value: 0x0: Interrupt mask write disabled 0x1: Interrupt mask write enabled
7:0	INT_MASK	RW	0x0	Mask for Source Transaction Complete Interrupt Value: 0x0: Mask the interrupts. 0x1: Unmask the interrupts.

INT_MASK_DTC

Name: Mask for Destination Transaction Complete Interrupt
Description: The contents of the raw status register INT_RSTAT_DTC are masked with the contents of the mask register INT_MASK_DTC. This register has a bit allocated to each channel; for example, INT_MASK_DTC[2] is the mask bit for the Channel 2 destination transaction complete interrupt. When the destination peripheral of DMA channel i is memory, then the destination transaction complete interrupt, INT_MASK_DTC[i], must be masked to prevent an erroneous triggering of an interrupt on the int_combined(_n) signal. A channel INT_MASK bit will be written only if the corresponding mask write enable bit in the INT_MASK_WE field is asserted on the same AHB write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, writing hex 01x1 to the INT_MASK_DTC register writes a 1 into INT_MASK_DTC[0], while INT_MASK_DTC[7:1] remains unchanged. Writing hex 00xx leaves INT_MASK_DTC[7:0] unchanged. Writing a 1 to any bit in this register unmasks the corresponding interrupt, thus allowing the DMA to set the appropriate bit in the status registers and int_port signals.
Base Address: 0x40013000
Offset: 0x328
Reset Value: 0x0

表 778 Mask for Destination Transaction Complete Interrupt
Bits	Field Name	RW	Reset	Description
63:16	RSVD_INT_MASK_DTC	R	0x0	Reserved field
15:8	INT_MASK_WE	W	0x0	Interrupt Mask Write Enable Value: 0x0: Interrupt mask write disabled 0x1: Interrupt mask write enabled
7:0	INT_MASK	RW	0x0	Mask for Destination Transaction Complete Interrupt Value: 0x0: Mask the interrupts. 0x1: Unmask the interrupts.

INT_MASK_ERR

Name: Mask for Error Interrupt
Description: The contents of the raw status register INT_RSTAT_ERR are masked with the contents of the mask register INT_MASK_ERR. This register has a bit allocated to each channel; for example, INT_MASK_ERR[2] is the mask bit for the Channel 2 error interrupt. A channel INT_MASK bit will be written only if the corresponding mask write enable bit in the INT_MASK_WE field is asserted on the same AHB write transfer. This allows software to set a mask bit without performing a read-modified write operation. For example, writing hex 01x1 to the INT_MASK_ERR register writes a 1 into INT_MASK_ERR[0], while INT_MASK_ERR[7:1] remains unchanged. Writing hex 00xx leaves INT_MASK_ERR[7:0] unchanged. Writing a 1 to any bit in this register unmasks the corresponding interrupt, thus allowing the DMA to set the appropriate bit in the Status registers and int_port signals.
Base Address: 0x40013000
Offset: 0x330
Reset Value: 0x0

表 779 Mask for Error Interrupt
Bits	Field Name	RW	Reset	Description
63:16	RSVD_INT_MASK_ERR	R	0x0	Reserved field
15:8	INT_MASK_WE	W	0x0	Interrupt Mask Write Enable Value: 0x0: Interrupt mask write disabled 0x1: Interrupt mask write enabled
7:0	INT_MASK	RW	0x0	Mask for Error Interrupt Value: 0x0: Mask the interrupts. 0x1: Unmask the interrupts.

INT_CLR_TC

Name: Clear for Transfer Complete Interrupt
Description: Each bit in the INT_RSTAT_TC and INT_STAT_TC is cleared on the same cycle by writing a 1 to the corresponding location in the registers. This register has a bit allocated to each channel; for example, INT_CLR_TC[2] is the clear bit for the Channel 2 transfer done interrupt. Writing a 0 has no effect. This register is not readable.
Base Address: 0x40013000
Offset: 0x338
Reset Value: 0x0

表 780 Clear for Transfer Complete Interrupt
Bits	Field Name	RW	Reset	Description
63:8	RSVD_INT_CLR_TC	W	0x0	Reserved field
7:0	CLR	W	0x0	Clear for Transfer Complete Interrupt Value: 0x0: No effect 0x1: Clears interrupts.

INT_CLR_BTC

Name: Clear for Block Transfer Complete Interrupt
Description: Each bit in the INT_RSTAT_BTC and INT_STAT_BTC is cleared on the same cycle by writing a 1 to the corresponding location in the registers. This register has a bit allocated to each channel; for example, INT_CLR_BTC[2] is the clear bit for the Channel 2 block done interrupt. Writing a 0 has no effect. This register is not readable.
Base Address: 0x40013000
Offset: 0x340
Reset Value: 0x0

表 781 Clear for Block Transfer Complete Interrupt
Bits	Field Name	RW	Reset	Description
63:8	RSVD_INT_CLR_BTC	W	0x0	Reserved field
7:0	CLR	W	0x0	Clear for Block Transfer Complete Interrupt

INT_CLR_STC

Name: Clear for Source Transaction Complete Interrupt
Description: Each bit in the INT_RSTAT_STC and INT_STAT_STC is cleared on the same cycle by writing a 1 to the corresponding location in the registers. This register has a bit allocated to each channel; for example, INT_CLR_STC[2] is the clear bit for the Channel 2 source transaction done interrupt. Writing a 0 has no effect. This register is not readable.
Base Address: 0x40013000
Offset: 0x348
Reset Value: 0x0

表 782 Clear for Source Transaction Complete Interrupt
Bits	Field Name	RW	Reset	Description
63:8	RSVD_INT_CLR_STC	W	0x0	Reserved field
7:0	CLR	W	0x0	Clear for Source Transaction Complete Interrupt Value: 0x0: No effect 0x1: Clears interrupts.

INT_CLR_DTC

Name: Clear for Destination Transaction Complete Interrupt
Description: Each bit in the INT_RSTAT_DTC and INT_STAT_DTC is cleared on the same cycle by writing a 1 to the corresponding location in the registers. This register has a bit allocated to each channel; for example, INT_CLR_DTC[2] is the clear bit for the Channel 2 destination transaction done interrupt. Writing a 0 has no effect. This register is not readable.
Base Address: 0x40013000
Offset: 0x350
Reset Value: 0x0

表 783 Clear for Destination Transaction Complete Interrupt
Bits	Field Name	RW	Reset	Description
63:8	RSVD_INT_CLR_DTC	W	0x0	Reserved field
7:0	CLR	W	0x0	Clear for Destination Transaction Complete Interrupt Value: 0x0: No effect 0x1: Clears interrupts.

INT_CLR_ERR

Name: Clear for Error Interrupt
Description: Each bit in the INT_RSTAT_ERR and INT_STAT_ERR is cleared on the same cycle by writing a 1 to the corresponding location in the registers. This register has a bit allocated to each channel; for example, INT_CLR_ERR[2] is the clear bit for the Channel 2 error interrupt. Writing a 0 has no effect. This register is not readable.
Base Address: 0x40013000
Offset: 0x358
Reset Value: 0x0

表 784 Clear for Error Interrupt
Bits	Field Name	RW	Reset	Description
63:8	RSVD_INT_CLR_ERR	W	0x0	Reserved field
7:0	CLR	W	0x0	Clear for Error Interrupt Value: 0x0: No effect 0x1: Clears interrupts.

INT_STAT_ET

Name: Status for Each Interrupt Type
Description: The contents of each of the five status registers INT_STAT_TC, INT_STAT_BTC, INT_STAT_STC, INT_STAT_DTC, and INT_STAT_ERR are ORed to produce a single bit for each interrupt type in the combined status register (INT_STAT_ET). This register is read-only.
Base Address: 0x40013000
Offset: 0x360
Reset Value: 0x0

表 785 Status for Each Interrupt Type
Bits	Field Name	RW	Reset	Description
63:5	RSVD_INT_STAT_ET	R	0x0	Reserved field
4	ERR	R	0x0	OR of the contents of INT_STAT_ERR Value: 0x0: OR of the contents of INT_STAT_ERR register is 0. 0x1: OR of the contents of INT_STAT_ERR register is 1.
3	DEST_XFE_CPLT	R	0x0	OR of the contents of INT_STAT_DTC Value: 0x0: OR of the contents of INT_STAT_DTC register is 0. 0x1: OR of the contents of INT_STAT_DTC register is 1.
2	SRC_XFE_CPLT	R	0x0	OR of the contents of INT_STAT_STC Value: 0x0: OR of the contents of INT_STAT_STC register is 0. 0x1: OR of the contents of INT_STAT_STC register is 1.
1	BLK_XFE_CPLT	R	0x0	OR of the contents of INT_STAT_BTC register Value: 0x0: OR of the contents of INT_STAT_BTC register is 0. 0x1: OR of the contents of INT_STAT_BTC register is 1.
0	XFE_CPLT	R	0x0	OR of the contents of INT_STAT_TC register Value: 0x0: OR of the contents of INT_STAT_TC register is 0. 0x1: OR of the contents of INT_STAT_TC register is 1.

Software_Handshake_Registers

REQ_SST

Name: Source Software Transaction Request Register
Description: A bit is assigned for each channel in this register. REQ_SST[n] is ignored when software handshaking is not enabled for the source of channel n. A channel SRC_REQ bit is written only if the corresponding channel write enable bit in the SRC_REQ_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN register. For example, writing hex 0101 writes a 1 into REQ_SST[0], while REQ_SST[7:1] remains unchanged. Writing hex 00xx leaves REQ_SST[7:0] unchanged. This allows software to set a bit in the REQ_SST register without performing a read-modified write operation.
Base Address: 0x40013000
Offset: 0x368
Reset Value: 0x0

表 786 Source Software Transaction Request Register
Bits	Field Name	RW	Reset	Description
63:16	Rsvd_1_REQ_SST	R	0x0	Reserved field
15:8	SRC_REQ_WE	RW	0x0	Source Software Transaction Request write enable Value: 0x0: Source request write disabled 0x1: Source request write enabled
7:0	SRC_REQ	RW	0x0	Source Software Transaction Request Value: 0x0: Source request is not active. 0x1: Source request is active.

REQ_DST

Name: Destination Software Transaction Request Register
Description: A bit is assigned for each channel in this register. REQ_DST[n] is ignored when software handshaking is not enabled for the source of channel n. A channel DEST bit is written only if the corresponding channel write enable bit in the DEST_REQ_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN register.
Base Address: 0x40013000
Offset: 0x370
Reset Value: 0x0

表 787 Destination Software Transaction Request Register
Bits	Field Name	RW	Reset	Description
63:16	Rsvd_1_REQ_DST	R	0x0	Reserved field
15:8	DEST_REQ_WE	RW	0x0	Destination Software Transaction Request write enable Value: 0x0: Destination request write disabled 0x1: Destination request write enabled
7:0	DEST_REQ	RW	0x0	Destination Software Transaction Request Value: 0x0: Destination request is not active. 0x1: Destination request is active.

REQ_SGL_ST

Name: Source Single Transaction Request Register
Description: A bit is assigned for each channel in this register. REQ_SGL_ST is ignored when software handshaking is not enabled for the source of channel n. A channel SRC_SGL_REQ bit is written only if the corresponding channel write enable bit in the SRC_SGL_REQ_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN register.
Base Address: 0x40013000
Offset: 0x378
Reset Value: 0x0

表 788 Source Single Transaction Request Register
Bits	Field Name	RW	Reset	Description
63:16	Rsvd_1_REQ_SGL_ST	R	0x0	Reserved field
15:8	SRC_SGL_REQ_WE	RW	0x0	Source Single Transaction Request write enable Value: 0x0: Single write disabled 0x1: Single write enabled
7:0	SRC_SGL_REQ	RW	0x0	Source Single Transaction Request Value: 0x0: Source request is not active. 0x1: Source request is active.

REQ_SGL_DT

Name: Destination Single Transaction Request Register
Description: A bit is assigned for each channel in this register. REQ_SGL_DT is ignored when software handshaking is not enabled for the destination of channel n. A channel DEST_SGL_REQ bit is written only if the corresponding channel write enable bit in the DST_SGL_REQ_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN register.
Base Address: 0x4A0013000
Offset: 0x380
Reset Value: 0x0

表 789 Destination Single Transaction Request Register
Bits	Field Name	RW	Reset	Description
63:16	Rsvd_1_REQ_SGL_DT	R	0x0	Reserved field
11:8	DST_SGL_REQ_WE	RW	0x0	Destination Single Transaction Request write enable Value: 0x0: Destination write disabled 0x1: Destination write enabled
7:0	DEST_SGL_REQ	RW	0x0	Destination Single Transaction Request Value: 0x0: Destination single or burst request is not active. 0x1: Destination single or burst request is active.

REQ_LST_ST

Name: Source Last Transaction Request Register
Description: A bit is assigned for each channel in this register. REQ_LST_ST is ignored when software handshaking is not enabled for the source of channel n, or when the source of channel n is not a flow controller. A channel LST_SRC bit is written only if the corresponding channel write enable bit in the LST_SRC_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN register.
Base Address: 0x40013000
Offset: 0x388
Reset Value: 0x0

表 790 Source Last Transaction Request Register
Bits	Field Name	RW	Reset	Description
63:16	Rsvd_1_REQ_LST_ST	R	0x0	Reserved field
15:8	LST_SRC_WE	RW	0x0	Source Last Transaction Request write enable Value: 0x0: Source last transaction request write disabled 0x1: Source last transaction request write enabled
7:0	LST_SRC	RW	0x0	Source Last Transaction Request register Value: 0x0: Not last transaction in current block 0x1: Last transaction in current block

REQ_LST_DT

Name: Destination Last Transaction Request Register
Description: A bit is assigned for each channel in this register. REQ_LST_DT is ignored when software handshaking is not enabled for the destination of channel n or when the destination of channel n is not a flow controller. A channel LST_DEST bit is written only if the corresponding channel write enable bit in the LST_DEST_WE field is asserted on the same AHB write transfer, and if the channel is enabled in the CH_EN register.
Base Address: 0x40013000
Offset: 0x390
Reset Value: 0x0

表 791 Destination Last Transaction Request Register
Bits	Field Name	RW	Reset	Description
63:16	Rsvd_1_REQ_LST_DT	R	0x0	Reserved field
15:8	LST_DEST_WE	RW	0x0	Destination Last Transaction Request write enable Value: 0x0: Destination last transaction request write disabled 0x1: Destination last transaction request write enabled
7:0	LST_DEST	RW	0x0	Destination Last Transaction Request Value: 0x0: Not last transaction in current block 0x1: Last transaction in current block

Miscellaneous_Registers

CFG

Name: DMA Configuration Register
Description: This register is used to enable the DMA, which must be done before any channel activity. If the global channel enable bit is cleared while any channel is still active, CFG.DMA_EN still returns 1 to indicate that there are channels still active until hardware has terminated all activities on all channels, at which point the CFG.DMA_EN bit returns 0.
Base Address: 0x40013000
Offset: 0x398
Reset Value: 0x0

表 792 DMA Configuration Register
Bits	Field Name	RW	Reset	Description
63:1	RSVD_CFG	R	0x0	Reserved field
0	DMA_EN	RW	0x0	DMA Enable bit. Value: 0x0: DMA disabled 0x1: DMA enabled

CH_EN

Name: DMA Channel Enable Register
Description: This is the DMA Channel Enable Register. If software needs to set up a new channel, it can read this register in order to find out which channels are currently inactive; it can then enable an inactive channel with the required priority. All bits of this register are cleared to 0 when the global DMA channel enable bit, CFG[0], is 0. When the global channel enable bit is 0, a write to the CH_EN register is ignored and a read will always read back 0. The channel enable bit, CH_EN.CH_EN, is written only if the corresponding channel write enable bit, CH_EN.CH_EN_WE, is asserted on the same AHB write transfer. For example, writing hex 01x1 writes a 1 into CH_EN[0], while CH_EN[7:1] remains unchanged. Writing hex 00xx leaves CH_EN[7:0] unchanged. Note that a read-modified write is not required.
Base Address: 0x40013000
Offset: 0x3a0
Reset Value: 0x0

表 793 DMA Channel Enable Register
Bits	Field Name	RW	Reset	Description
63:16	Rsvd_1_CH_EN	R	0x0	Reserved field
15:8	CH_EN_WE	W	0x0	Channel enable register
7:0	CH_EN	RW	0x0	Channel Enable. The CH_EN.CH_EN bit is automatically cleared by hardware to disable the channel after the last AMBA transfer of the DMA transfer to the destination has completed. Software can therefore poll this bit to determine when this channel is free for a new DMA transfer. Value: 0x0: Disable the channel. 0x1: Enable the channel.

Registers

Channel_x_Registers

SARx

DARx

LLPx

CTLx

SSTATx

DSTATx

SSTATARx

DSTATARx

CFGx

SGRx

DSRx

Interrupt_Registers

INT_RSTAT_TC

INT_RSTAT_BTC

INT_RSTAT_STC

INT_RSTAT_DTC

INT_RSTAT_ERR

INT_STAT_TC

INT_STAT_BTC

INT_STAT_STC

INT_STAT_DTC

INT_STAT_ERR

INT_MASK_TC

INT_MASK_BTC

INT_MASK_STC

INT_MASK_DTC

INT_MASK_ERR

INT_CLR_TC

INT_CLR_BTC

INT_CLR_STC

INT_CLR_DTC

INT_CLR_ERR

INT_STAT_ET

Software_Handshake_Registers

REQ_SST

REQ_DST

REQ_SGL_ST

REQ_SGL_DT

REQ_LST_ST

REQ_LST_DT

Miscellaneous_Registers

CFG

CH_EN

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