Always-On I/O
Introduction
A GR5526 SoC has eight individually configurable AON_GPIOs that can be applied by peripherals or digital input/output.
Functional Description
For all AON_GPIOs,
- The I/O default state is input mode with pull-down.
- Can be configured as being triggered by high level, low level, rising edge, falling edge, or both edges
- Can work as wake-up sources from deep sleep.
- Can generate slow-speed clocks.
- Can work as digital GPIOs for input/output.
- Can be multiplexed for different peripherals.
Registers
AON_PAD_CTRL0
- Name: Always-on Pad Control Register
- Description: This register contains the AON_GPIO configurations.
- Base Address: 0x4000A000
- Offset: 0x1E8
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:16 |
RSVD |
R |
Reserved bits |
|
15:8 |
AON_R_TYPE |
RW |
0x0 |
Always-on PAD resistor type Value:
|
7:0 |
AON_RE_N |
RW |
0x0 |
Always-on PAD resister enable Value:
|
AON_PAD_CTRL1
- Name: Always-on Pad Control Register
- Description: This register contains the input and output data.
- Base Address: 0x4000A000
- Offset: 0x1EC
- Reset Value: 0x000000FF
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:24 |
RSVD |
R |
Reserved bits |
|
23:16 |
AON_INPUT_VAL |
RW |
0x0 |
AON pad input value (valid when oe_n = 1) Value:
|
15:8 |
AON_OUT_VAL |
RW |
0x0 |
AON PAD output value (valid when oe_n = 0) Value:
|
7:0 |
AON_O_N |
RW |
0xFF |
Always-on pad output enable (active low) Value:
|
AON_PAD_CLK
- Name: Always-on PAD output clock controls register
- Description: This register controls inner clock output from AON_GPIO_4.
- Base Address: 0x4000A000
- Offset: 0x1F0
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:5 |
RSVD |
R |
Reserved bits |
|
4:2 |
CLK_OUT_SEL |
RW |
0x0 |
Clock out selection Value:
|
1 |
RSVD |
R |
Reserved bits |
|
0 |
CLK_OUT_EN |
RW |
0x0 |
Enable clock out via AON GPIO 4. Value:
|
AON_PAD_MCU_OVR
- Name: Always-on Pad Control Register
- Description: This register controls the MCU domain setting of always-on pads.
- Base Address: 0x4000A000
- Offset: 0x1F4
- Reset Value: 0x000000FF
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:17 |
RSVD |
R |
Reserved bits |
|
23:16 |
AON_PAD_MCU_OVR |
RW |
0x0 |
Use the settings from MCU domain; only valid when MCU domain is ON
|
15:0 |
RSVD |
R |
Reserved bits |
Electrical Specifications
The electrical parameters for the AON_GPIO_0–AON_GPIO_7 are as follows:
| Parameter | Description | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|
|
VIH |
Input high voltage |
VDDIO x 0.7 |
VDDIO |
V |
|
|
VIL |
Input low voltage |
VSSIO |
VDDIO x 0.3 |
V |
|
|
VOH,L |
Output high voltage, 4 mA, VDDIO ≥ 1.7 V |
VDDIO – 0.4 |
VDDIO |
V |
|
|
VOH,M |
Output high voltage, 4 mA, VDDIO ≥ 2.5 V |
VDDIO – 0.4 |
VDDIO |
V |
|
|
VOH,H |
Output high voltage, 4 mA, VDDIO ≥ 3 V |
VDDIO – 0.4 |
VDDIO |
V |
|
|
VOL,L |
Output low voltage, 4 mA, VDDIO ≥ 1.7 V |
VSS |
VSS + 0.4 |
V |
|
|
VOL,M |
Output low voltage, 4 mA, VDDIO ≥ 2.5 V |
VSS |
VSS + 0.4 |
V |
|
|
VOL,H |
Output low voltage, 4 mA, VDDIO ≥ 3 V |
VSS |
VSS + 0.4 |
V |
|
|
IOL,L |
Current at VSS+0.4 V, output set low, VDDIO ≥1.7 V |
4 |
mA |
||
|
IOL,M |
Current at VSS+0.4 V, output set low, VDDIO ≥ 2.5 V |
5 |
mA |
||
|
IOH,L |
Current at VDD-0.4 V, output set high, VDDIO ≥ 1.7 V |
4 |
mA |
||
|
IOH,M |
Current at VDD-0.4 V, output set high, VDD ≥ 2.5 V |
5 |
mA |
||
|
tRF,15pF |
Rise/Fall time, 10%–90%, 15 pF load |
5 |
8 |
ns |
|
|
tRF,25pF |
Rise/Fall time, 10%–90%, 25 pF load |
6 |
13 |
ns |
|
|
RPU |
Pull-up resistance |
70 |
120 |
150 |
kΩ |
|
RPD |
Pull-down resistance |
70 |
120 |
150 |
kΩ |
|
CPAD |
Pad capacitance |
5 |
pF |
