Interrupt
In addition to supporting 16 system exceptions within the ARM® Cortex®-M4F, the GR5526 series also supports 66 external interrupts with 256 programmable priority levels. In some cases, a single peripheral may be able to generate multiple different interrupts (such as BOD/BLE). Most interrupts are connected directly to the NVIC, but all wakeup sources on the always-on domain are connected to the Power State Controller (PSC) outside of the ARM® Cortex®-M4F, allowing the interrupt sources to wake up the ARM® Cortex®-M4F core from the deep sleep mode. In most cases, developers do not need to change the interrupt source.
The Cortex®-M4F allows developers to assign various interrupts to different priority levels based on the application requirements. In order to maintain the stability of Bluetooth connection, it is recommended that the priority of Bluetooth interrupt should be configured to be the highest. In most cases, developers do not need to change priority levels, and the GR5526 SoCs have been configured with default priorities to meet most application requirements.
One additional feature of the Cortex®-M4F interrupt architecture is the ability to relocate the vector table to different addresses. The software can move the vector table into SRAM and reassign the interrupt service routine entry addresses on demand, but it should be noted that the remapping start address of the interrupt vector table should be aligned with 0x200. For example, the vector table base address should be set as 0x00000000, 0x00000200, or 0x00000400.
All non-programmable and programmable interrupts including those that can wake the MCU up from deep sleep mode are shown in 表 8 and 表 9. The width of interrupt priority control register is 8 bits, in which bit7 to bit4 are used for preemption priority and bit3 to bit0 are used for subpriority.
| No. | Name | Default Priority | Waking up MCU | Description |
|---|---|---|---|---|
| 1 | Reset_IRQ | -3 | Reset exception | |
| 2 | NMI_IRQn | -2 | Non-maskable interrupt | |
| 3 | HardFault_IRQ | -1 | All classes of fault. This interrupt occurs when the corresponding fault handler cannot be activated because it is currently disabled or masked by exception masking. |
| No. | Name | Default Preemption Priority | Default Subpriority | Waking up MCU | Description |
|---|---|---|---|---|---|
| 4 | MemManage_IRQ | - | - | Memory management fault; caused by MPU violation or invalid accesses | |
| 5 | BusFault_IRQ | - | - | Error response received from the bus system | |
| 6 | UsageFault_IRQ | - | - | Usage fault; typical causes are invalid instructions or invalid state transition attempts. | |
| 7–10 | Reserved | - | - | Unused | |
| 11 | SVCall_IRQ | 0 | 0 | Supervisor call via SVC instruction | |
| 12 | DebugMonitor_IRQ | - | - | Debug monitor – for software-based debugging | |
| 13 | Reserved | - | - | Unused | |
| 14 | PendSV_IRQ | 15 | 15 | Pendable request for system service | |
| 15 | SysTick_IRQ | 15 | 15 | System tick timer interrupt | |
| 16 | Reserved | - | - | Reserved | |
| 17 | BLE_SDK_IRQ | 15 | 15 | BLE software development kit (SDK) schedule interrupt | |
| 18 | BLE_IRQ | 2 | 0 | √ | BLE interrupt |
| 19 | DMA0_IRQ | 6 | 0 | DMA0 interrupt | |
| 20 | SPI_M_IRQ | 8 | 0 | SPI master interrupt | |
| 21 | SPI_S_IRQ | 8 | 0 | SPI slave interrupt | |
| 22 | EXT0_IRQ | 8 | 0 | GPIO_0 interrupt | |
| 23 | EXT1_IRQ | 8 | 0 | GPIO_1 interrupt | |
| 24 | TIMER0_IRQ | 12 | 0 | TIMER0 interrupt | |
| 25 | TIMER1_IRQ | 12 | 0 | TIMER1 interrupt | |
| 26 | DUAL_TIMER_IRQ | 12 | 0 | DUAL_TIMER interrupt | |
| 27 | QSPI0_IRQ | 8 | 0 | QSPI0 interrupt | |
| 28 | UART0_IRQ | 10 | 0 | UART0 interrupt | |
| 29 | UART1_IRQ | 10 | 0 | UART1 interrupt | |
| 30 | I2C0_IRQ | 8 | 0 | I2C0 interrupt | |
| 31 | I2C1_IRQ | 8 | 0 | I2C1 interrupt | |
| 32 | AES_IRQ | 8 | 0 | AES interrupt | |
| 33 | HMAC_IRQ | 8 | 0 | HMAC interrupt | |
| 34 | EXT2_IRQ | 8 | 0 | GPIO_2 interrupt | |
| 35 | RNG_IRQ | 8 | 0 | TRNG interrupt | |
| 36 | BOD_ASSERT_IRQ | 8 | 0 | Brown-out detect interrupt | |
| 37 | PKC_IRQ | 8 | 0 | PKC interrupt | |
| 38 | XQSPI_IRQ | 8 | 0 | XQSPI interrupt | |
| 39 | QSPI1_IRQ | 8 | 0 | QSPI1 interrupt | |
| 40 | OSPI_IRQ | 8 | 0 | OSPI interrupt | |
| 41 | BLESLP_IRQ | 2 | 0 | √ | BLE timer done interrupt |
| 42 | SLPTIMER_IRQ | 12 | 0 | √ | Sleep timer done interrupt |
| 43 | AON_EXT_IRQ | 8 | 0 | √ | AON GPIO interrupt |
| 44 | AON_WDT_IRQ | 8 | 0 | √ | AON watch dog timer interrupt |
| 45 | I2S_M_IRQ | 8 | 0 | I2S master interrupt | |
| 46 | I2S_S_IRQ | 8 | 0 | I2S slave interrupt | |
| 47 | ISO7816_IRQ | 8 | 0 | SIM card interrupt | |
| 48 | PRESENT_IRQ | 8 | 0 | Present done interrupt | |
| 49 | RTC0_IRQ | 8 | 0 | √ | Real-timer counter0 interrupt |
| 50 | COMM_CORE_IRQ | 8 | 0 | Communication core | |
| 51 | DMA1_IRQ | 6 | 0 | DMA1 interrupt | |
| 52 | DMA2_IRQ | 6 | 0 | DMA2 interrupt | |
| 53 | DSPI_IRQ | 8 | 0 | DSPI interrupt | |
| 54 | AON_IRQ | 8 | 0 | AON domain interrupt | |
| 55 | PDM_IRQ | 8 | 0 | PDM interrupt | |
| 56 | VTTBL_IRQ | 8 | 0 | VT table interrupt | |
| 57 | CTE_FULL_IRQ | 8 | 0 | CTE full interrupt | |
| 58 | USB_IRQ | 8 | 0 | USB interrupt | |
| 59 | TSI_DC_IRQ | 8 | 0 | Display control interrupt | |
| 60 | BOD_DEASSERT_IRQ | 8 | 0 | √ | Brown out detect disappear interrupt |
| 61 | COMP_IRQ | 8 | 0 | √ | Comparator interrupt |
| 62 | USB_ATTACH_IRQ | 8 | 0 | √ | USB attach interrupt |
| 63 | USB_DETACH_IRQ | 8 | 0 | √ | USB detach interrupt |
| 64 | RTC1_IRQ | 8 | 0 | √ | Real-timer counter1 interrupt |
| 65 | CPLL_DRIFT_IRQ | 8 | 0 | CPLL drift interrupt | |
| 66 | CLK_CALIB_IRQ | 8 | 0 | Clock calibration0/1 interrupt | |
| 67 | TSI_GPU_IRQ | 8 | 0 | GPU interrupt | |
| 68 | UART2_IRQ | 10 | 0 | UART2 interrupt | |
| 69 | UART3_IRQ | 10 | 0 | UART3 interrupt | |
| 70 | UART4_IRQ | 10 | 0 | UART4 interrupt | |
| 71 | UART5_IRQ | 10 | 0 | UART5 interrupt | |
| 72 | BLE_PWR_ON_IRQ | 2 | 0 | BLE sequencer power on done interrupt | |
| 73 | BLE_PWR_DN_IRQ | 8 | 0 | BLE sequencer power off done interrupt | |
| 74 | I2C2_IRQ | 8 | 0 | I2C2 interrupt | |
| 75 | I2C3_IRQ | 8 | 0 | I2C3 interrupt | |
| 76 | I2C4_IRQ | 8 | 0 | I2C4 interrupt | |
| 77 | I2C5_IRQ | 8 | 0 | I2C5 interrupt | |
| 78 | XO_BIAS_SW_CHG_IRQ | 8 | 0 | Crystal oscillator (XO) bias switch changed interrupt | |
| 79 | AVS_ERR_IRQ | 8 | 0 | AVS control error interrupt | |
| 80 | TSI_GPU_ERR_IRQ | 8 | 0 | GPU error interrupt | |
| 81 | QSPI2_IRQ | 8 | 0 | QSPI2 interrupt |
