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文档中心 > GR5526 Datasheet/ MCU Core/ Functional Overview Copy URL

Functional Overview

The GR5526 core includes on-chip OSPI PSRAM, built-in XIP FLASH, and high-performance 32-bit ARM® Cortex®-M4F processor. In addition, the GR5526 core has a series of high-speed peripherals such as digital communication, analog interface, and IO. For details, see Peripherals.

The Cortex®-M4F is built on a high-performance processor core with a 3-stage pipeline Harvard architecture, making it ideal for demanding embedded applications. The processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including optional IEEE754-compliant single-precision floating-point computation, a range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedicated hardware division.

To facilitate the design of cost-sensitive devices, the Cortex®-M4F processor implements tightly-coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex®-M4F processor implements a version of the Thumb® instruction set based on Thumb-2 technology, ensuring high code density and reduced program memory requirements. The Cortex®-M4F instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers.

The Cortex®-M4F processor closely integrates a configurable Nested Vectored Interrupt Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC includes a Non Maskable Interrupt (NMI) that can provide up to 256 interrupt priority levels. The tight integration of the processor core and NVIC provides fast execution of Interrupt Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require wrapping in assembler code, removing any code overhead from the ISRs. A tail-chain optimization also significantly reduces the overhead when switching from one ISR to another.

The Cortex®-M4F processors include many debug features that allow developers to analyze design problems easily. Besides standard design features which developers can find in most microcontrollers like halting and single stepping, developers can also generate a trace to capture program flow, data changes, profiling information, and more.

The ARM® Cortex®-M4F processor offers a number of CPU options and support modules implemented on the device.

表 6 Support modules
No. Option/Module Description Implemented

1

NVIC

Nested vector interrupt controller

66 vectors

2

PRIORITIES

Priority bits

8 bits

3

Endianness

Memory system endianness

Little endian

4

Bit-banding

Bit banded memory

Yes

5

DWT

Data watchpoint and trace

Yes

6

SysTick

System tick timer

Yes

7

FPU

Floating-point unit

Yes

8

MPU

Memory protection unit

8 regions

9

DAP

Debug access port

Yes

10

ETM

Embedded trace macrocell

No

11

ITM

Instrumentation trace macrocell

Yes

12

TPIU

Trace port interface unit

Yes

13

ETB

Embedded trace buffer

No

14

FPB

Flash patch and breakpoint unit

16 addresses

Benefiting from the efficient design of each module, GR5526 can easily reach a high level of operating efficiency. The CoreMark score is shown in the table below.

表 7 MCU CoreMark score
Symbol Description Min. Typ. Max. Unit
CMFLASH CoreMark, running from Flash, 96 MHz, direct map cache 316 CoreMark
CMFLASH/MHz CoreMark per MHz, running from Flash, 96 MHz, direct map cache 3.3 CoreMark/MHz
CMFLASH CoreMark, running from Flash, 96 MHz, 4-way associative cache 261 CoreMark
CMFLASH/MHz CoreMark per MHz, running from Flash, 96 MHz, 4-way associative cache 2.7 CoreMark/MHz

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