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文档中心 > GR5526 Datasheet/ Peripherals/ Pin Mux/ Functional Description Copy URL

Functional Description

The pin multiplexing choices for all pads are shown in:

There are eight mux choices (from MUX_0 to MUX_7) in the pin mux tables as follows.

表 132 Pin multiplexing for GPIO_0–GPIO_7
IO Name MUX_0 MUX_1 MUX_2 MUX_3 MUX_4 MUX_5 MUX_6 MUX_7

GPIO_0

SWD_CLK

I2C1_SCL

UART0_TX

UART1_CTS

PWM1_C

PWM0_C

PDM_CLKO

GPIO_A0

GPIO_1

SWD_IO

I2C1_SDA

UART0_RX

UART1_RTS

PWM1_B

PWM0_B

PDM_DI

GPIO_A1

GPIO_2

I2C0_SCL

PDM_CLKO

UART0_CTS

UART1_TX

PWM1_A

PWM0_A

iso_sync1_p

GPIO_A2

GPIO_3

I2C0_SDA

PDM_DI

UART0_RTS

UART1_RX

FERP_GPIO_Trig

SWV

iso_sync0_p

GPIO_A3

GPIO_4

I2C4_SCL

SPI_M_CLK

PWM0_A

UART3_TX

PDM_CLKO

df_ant_switch_sel_0

UART2_CTS

GPIO_A4

GPIO_5

I2C4_SDA

SPI_M_MOSI

PWM0_B

UART3_RX

PDM_DI

df_ant_switch_sel_1

UART2_RTS

GPIO_A5

GPIO_6

I2C3_SCL

SPI_M_MISO

PWM0_C

I2S_WS

iso_sync1_p

SPI_S_CLK

SIM_PRESENCE

GPIO_A6

GPIO_7

I2C3_SDA

SPI_M_CS0_N

PWM1_A

I2S_TX_SDO

iso_sync0_p

SPI_S_MISO

SIM_RST_N

GPIO_A7

表 133 Pin multiplexing for GPIO_8–GPIO_15
IO Name MUX_0 MUX_1 MUX_2 MUX_3 MUX_4 MUX_5 MUX_6 MUX_7

GPIO_8

I2C5_SCL

UART2_TX

PWM1_B

I2S_RX_SDI

UART3_CTS

SPI_S_MOSI

SIM_IO

GPIO_A8

GPIO_9

I2C5_SDA

UART2_RX

PWM1_C

I2S_SCLK

UART3_RTS

SPI_S_CS_N

SIM_CLK

GPIO_A9

GPIO_10

QSPI_M1_CS_N

I2S_S_WS

SPI_M_CS0_N

UART4_CTS

UART5_RX

PWM1_A

SPI_S_MOSI

GPIO_A10

GPIO_11

QSPI_M1_IO_3

I2S_S_TX_SDO

I2C3_SCL

UART4_RTS

UART5_TX

PWM1_B

SPI_S_CLK

GPIO_A11

GPIO_12

QSPI_M1_IO_2

I2S_S_RX_SDI

I2C3_SDA

UART4_TX

UART5_CTS

PWM1_C

SPI_S_MISO

GPIO_A12

GPIO_13

QSPI_M1_IO_1

I2S_S_SCLK

SPI_M_MISO

UART4_RX

UART5_RTS

FERP_GPIO_Trig

SPI_S_CS_N

GPIO_A13

GPIO_14

QSPI_M1_IO_0

I2C5_SCL

SPI_M_MOSI

PDM_CLKO

df_ant_switch_sel_2

UART0_TX

iso_sync1_p

GPIO_A14

GPIO_15

QSPI_M1_CLK

I2C5_SDA

SPI_M_CLK

PDM_DI

df_ant_switch_sel_3

UART0_RX

iso_sync0_p

GPIO_A15

表 134 Pin multiplexing for GPIO_16–GPIO_23
IO Name MUX_0 MUX_1 MUX_2 MUX_3 MUX_4 MUX_5 MUX_6 MUX_7

GPIO_16

QSPI_M2_CLK

DC_CLK

DSPI_SCK

SPI_M_CLK

UART4_TX

PWM0_C

I2C0_SCL

GPIO_B0

GPIO_17

QSPI_M2_IO_0

DC_IO_0

DSPI_MOSI

SPI_M_MOSI

UART2_TX

UART3_CTS

I2C0_SDA

GPIO_B1

GPIO_18

QSPI_M2_IO_1

DC_IO_1

DSPI_MISO

SPI_M_MISO

UART2_RX

UART3_RTS

PWM1_A

GPIO_B2

GPIO_19

QSPI_M2_IO_2

DC_IO_2

DSPI_DCX

SPI_M_CS0_N

UART2_CTS

UART3_TX

PWM1_B

GPIO_B3

GPIO_20

QSPI_M2_IO_3

DC_IO_3

DSPI_CSS

SPI_M_CS1_N

UART2_RTS

UART3_RX

PWM1_C

GPIO_B4

GPIO_21

QSPI_M0_CLK

SPI_M_CLK

SIM_CLK

I2S_SCLK

I2S_S_SCLK

SPI_S_CLK

I2C3_SCL

GPIO_B5

GPIO_22

QSPI_M0_IO_0

SPI_M_MOSI

SIM_IO

I2S_RX_SDI

I2S_S_TX_SDO

SPI_S_MISO

I2C3_SDA

GPIO_B6

GPIO_23

QSPI_M0_IO_1

SPI_M_MISO

SIM_RST_N

I2S_TX_SDO

I2S_S_RX_SDI

SPI_S_MOSI

I2C2_SCL

GPIO_B7

表 135 Pin multiplexing for GPIO_24–GPIO_33
IO Name MUX_0 MUX_1 MUX_2 MUX_3 MUX_4 MUX_5 MUX_6 MUX_7

GPIO_24

QSPI_M0_IO_2

SPI_M_CS0_N

SIM_PRESENCE

I2S_WS

I2S_S_WS

SPI_S_CS_N

I2C2_SDA

GPIO_B8

GPIO_25

QSPI_M0_IO_3

SPI_M_CS1_N

FERP_GPIO_Trig

UART4_RX

I2C3_SCL

I2C1_SCL

PWM0_A

GPIO_B9

GPIO_26

QSPI_M0_CS_N

SPI_M_CS0_N

UART0_CTS

SPI_M_CLK

I2C3_SDA

I2C1_SDA

PWM0_B

GPIO_B10

GPIO_27

QSPI_M2_CS_N

DC_CS_N

UART0_RTS

SPI_M_MOSI

I2C2_SCL

I2C0_SCL

PWM0_C

GPIO_B11

GPIO_28

PDM_CLKO

iso_sync1_p

UART0_TX

SPI_M_MISO

I2C2_SDA

I2C0_SDA

SPI_M_CLK

GPIO_B12

GPIO_29

PDM_DI

iso_sync0_p

UART0_RX

SPI_M_CS0_N

FERP_GPIO_Trig

DC_DCX

SPI_M_MOSI

GPIO_B13

GPIO_30

SPI_S_MOSI

I2S_SCLK

I2S_S_WS

I2C1_SCL

UART1_CTS

I2C5_SCL

SPI_M_MISO

GPIO_B14

GPIO_31

SPI_S_CLK

I2S_RX_SDI

I2S_S_TX_SDO

I2C1_SDA

UART1_RTS

I2C5_SDA

SPI_M_CS0_N

GPIO_B15

GPIO_32

SPI_S_MISO

I2S_TX_SDO

I2S_S_RX_SDI

PDM_CLKO

UART1_TX

PWM0_B

I2C0_SCL

GPIO_C0

GPIO_33

SPI_S_CS_N

I2S_WS

I2S_S_SCLK

PDM_DI

UART1_RX

PWM0_A

I2C0_SDA

GPIO_C1

表 136 Pin multiplexing for AON_GPIO_0–AON_GPIO_7
IO Name MUX_0 MUX_1 MUX_2 MUX_3 MUX_4 MUX_5 MUX_6 MUX_7

AON_GPIO_0

UART4_CTS

I2C4_SCL

PWM0_A

SIM_PRESENCE

PWM0_C

UART2_TX

AON_GPIO_0

AON_GPIO_1

UART4_RTS

I2C4_SDA

PWM0_B

SIM_RST_N

PWM1_A

UART2_RX

AON_GPIO_1

AON_GPIO_2

UART4_TX

I2C1_SCL

PWM0_C

SIM_IO

PWM1_B

iso_sync_p

AON_GPIO_2

AON_GPIO_3

UART4_RX

I2C1_SDA

PWM1_A

SIM_CLK

PWM1_C

AON_GPIO_3

AON_GPIO_4

PWM0_A

UART5_RX

I2C0_SCL

PWM1_B

SIM_CLK

coex_ble_tx

AON_GPIO_4

AON_GPIO_5

PWM0_B

UART5_TX

I2C0_SDA

PWM1_C

iso_sync_p

coex_ble_rx

AON_GPIO_5

AON_GPIO_6

PWM0_C

UART5_CTS

I2C5_SCL

PDM_CLKO

UART1_RX

coex_wlan_tx

AON_GPIO_6

AON_GPIO_7

PWM1_A

UART5_RTS

I2C5_SDA

PDM_DI

UART1_TX

coex_wlan_rx

AON_GPIO_7

表 137 Pin multiplexing for MSIO_0–MSIO_7
IO Name MUX_0 MUX_1 MUX_2 MUX_3 MUX_4 MUX_5 MUX_6 MUX_7

MSIO_0

PWM0_A

SIM_CLK

UART3_RX

I2S_SCLK

I2S_S_SCLK

PDM_DI

MSIO_A0

MSIO_1

PWM0_B

SIM_IO

UART3_TX

I2S_RX_SDI

I2S_S_RX_SDI

PDM_CLKO

MSIO_A1

MSIO_2

PWM0_C

SIM_RST_N

UART3_RTS

I2S_TX_SDO

I2S_S_TX_SDO

coex_wlan_rx

MSIO_A2

MSIO_3

PWM1_A

SIM_PRESENCE

UART3_CTS

I2S_WS

I2S_S_WS

coex_wlan_tx

MSIO_A3

MSIO_4

UART2_RTS

PWM1_B

I2C3_SDA

I2C0_SDA

coex_ble_rx

iso_sync0_p

MSIO_A4

MSIO_5

UART2_CTS

PWM1_C

I2C3_SCL

I2C0_SCL

coex_ble_tx

iso_sync1_p

MSIO_A5

MSIO_6

UART2_RX

PWM1_B

I2C4_SDA

I2C1_SDA

iso_sync0_p

MSIO_A6

MSIO_7

UART2_TX

PWM1_C

I2C4_SCL

I2C1_SCL

iso_sync1_p

MSIO_A7

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