Cache

The GR5526 cache supports:

4-way set associative map mode with LFU replacement policy
8 KB cache memory (DataRAM) and 16 bytes per cache line
Auto clock gating for power saving
Profiling counters

GR5526 has an 8 KB cache memory that supports two map modes: direct map and 4-way set associative map with least frequently used (LFU) replacement policy. Both instruction and data access towards Flash memory or XIP code regions can be cached. The cache memory is enabled by default, but can be disabled by setting CACHE_DIS bit in XF_CTRL register. When cache is disabled, the number of Flash reading increases significantly, thus increasing power consumption and reducing the access speed.

The cache consists of TagRAM and DataRAM. The TagRAM is used to match addresses, and DataRAM is used to cache data. One cache line has 128 bits (16 bytes) DataRAM to cache data. In direct map mode, there are 512 cache lines; in 4-way set associative mode, one way has 128 cache lines.

The cache includes profiling counters. To measure the performance (hit-rate) of a code-section, the built-in profiling counters should be enabled. Before the beginning of the section, start the profiling counters by resetting CLR_HITMISS bit in XF_CTRL register. At the end of the section, the number of cache hits and cache misses for the section can be read from XF_HIT_COUNT and XF_MISS_COUNT registers, and users can stop the counters by setting CLR_HITMISS bit. The cache hit-rate can be calculated based on the formula: XF_HIT_COUNT/(XF_HIT_COUNT + XF_MISS_COUNT). The XF_HIT_COUNT and XF_MISS_COUNT registers do not wrap around after reaching the maximum value. If the maximum value is reached, consider profiling for a shorter duration to get correct numbers.

Registers

XF_CTRL

Name: Cache Control Register
Description: Cache Control Register
Base address: 0x4000D000
Offset: 0x00
Reset value: 0x00000012

表 17 Cache Control Register
Bits	Field Name	RW	Reset	Description
31:12	RSVD	R		Reserved bits
11	DIREC_MAP	RW	0x0	Enable direct map. 0x0: 4-way associative map enabled 0x1: Direct map enabled (no effect for sequential access)
10	CLK_FORCE_EN_3	RW	0x0	Cache_FSM and cache memory clock gating 0x0: Forcibly disable gating. 0x1: Enable gating dynamically.
9	CLK_FORCE_EN_2	RW	0x0	APB clock gating control 0x0: Forcibly disable gating. 0x1: Enable gating dynamically.
8	CLK_FORCE_EN_1	RW	0x0	Cache CLK_96 gating control 0x0: Forcibly disable gating. 0x1: Enable gating dynamically.
7	CLK_FORCE_EN_0	RW	0x0	XQSPI and cache HCLK gating control 0x0: Forcibly disable gating. 0x1: Enable gating dynamically.
6	BUF_DIS	RW	0x0	Disable cache buffer preload. 0x0: Cache preload enabled 0x1: Cache preload disabled
5	DIS_SEQ_ACCESS	RW	0x0	Disable sequential cache access. 0x0: Cache sequential access enabled 0x1: Cache sequential access disabled
4	CLR_HITMISS	RW	0x1	Clear hit/miss counters. 0x0: Hit and miss counters in normal mode 0x1: Hit and miss counters in clear mode (default)
3	CLR_FIFO	RW	0x0	Clear LFU FIFO. 0x0: FIFO in normal mode (default) 0x1: FIFO in clear mode
2	RSVD	R	0x0	Reserved bit
1	TAG_MEM_FLUSH_EN	RW	0x1	Enable tag memory flush. Out of resetting tag memory will get flushed unless tag_ret is enabled (tag_ret signal lives in CPU register space). 0x0: Tag memory flush is disabled. 0x1: Tag memory flush is enabled.
0	CACHE_DIS	RW	0x1	Disable cache. 0x0: Cache enabled 0x1: Cache disabled (default)

XF_HIT_COUNT

Name: Cache Hit Count Register
Description: Cache hit counter
Base Address: 0x4000D000
Offset: 0x08
Reset Value: 0x00000000

表 18 Cache Hit Count Register
Bits	Field Name	RW	Reset	Description
31:0	CACHE_HIT_CNT	RO	0x0	Read cache hit count (If bit[4] of XF_CTRL is 0).

XF_MISS_COUNT

Name: Cache Miss Count Register
Description: Cache miss counter
Base Address: 0x4000D000
Offset: 0x0C
Reset Value: 0x00000000

表 19 Cache Miss Count Register
Bits	Field Name	RW	Reset	Description
31:0	CACHE_MISS_CNT	RO	0x0	Read cache miss count (If bit[4] of XF_CTRL is 0).

XF_STAT

Name: Cache Flush Status Register
Description: Read cache flush status.
Base Address: 0x4000D000
Offset: 0x10
Reset Value: 0x00000000