Memory Map

Referring to the Cortex^®-M processor storage architecture, a GR5526 SoC divides its memory into ROM, Flash, data memory, peripheral memory, and memory for debugging components. All the mapping spaces of the 4 GB SoC memory are shown in 图 4.

• The contents of the ROM area have been preprogrammed and cannot be modified by developers. This area mainly stores the startup process and code related to BLE protocol stack.
• The RAM Alias1 area is used to store special-purpose code segments that are generally used for Flash operations or to speed up code fetching. Due to the characteristics of the Cortex^®-M4F bus architecture, there are independent instruction bus (I-CODE) and data bus (D-CODE) in the address space of 0x0000 0000–0x1FFF FFFF. The two buses can be used to fetch instructions and data in parallel, and the address space of 0x2000 0000–0xDFFF FFFF has only one system bus (System) where fetching instructions and data can only be performed serially. Therefore, it is more efficient to put code segments and constants in the area of 0x0000 0000–0x1FFF FFFF.
• The ExFlash area is generally used to store user code. ExFlash area and ExFlash Alias area share the same physical address. In non-encryption mode, the code data in the ExFlash area can also be read by the corresponding area of ExFlash Alias. In encryption mode, firmware key is required to support reading the content of ExFlash, and data key is required to support reading the content of ExFlash Alias.
• The RAM area is generally used to store data and code copied from Flash. In the ARM^® Cortex^®-M4F architecture, the bit-band operations in the 0x2000 0000–0x200F FFFF and 0x4000 0000–0x400F FFFF are conducive to the atomic characteristics of data operations.
• QSPI0, QSPI1, QSPI2, and OSPI all support XIP mode. In this mode, the data space of Flash or PRSAM can be mapped to the memory, which allows for direct operations on the memory address. For external PSRAM solutions, the external PSRAM mounted on QSPI M1 XIP Alias1 can be combined with the memory of 0x2000 0000–0x2007 FFFF to form a continuous SRAM address space. For internal PSRAM solutions, the internal PSRAM mounted on OSPI XIP Alias can be combined with the 0x3000 0000 – 0x3007 FFFF memory area to form a continuous SRAM address space.