Mixed Signal I/O
Introduction
A GR5526 SoC has eight individually configurable MSIOs that can be applied by peripherals, digital input\output or analog input.
Functional Description
- MSIO default state is analog input mode.
- As analog input for sense ADC or Comparator.
- As digital MSIOs for input/output, no interrupt.
- To multiplex some different peripherals.
- For digital modules with high timing requirements, it is recommended to increase the MSIO drive current.
Registers
MSIO_A_PAD_CFG0
- Name: MSIOA Pad Control Register
- Description: This register contains the input and output data.
- Base Address: 0x 4000A1D8
- Offset: 0x00
- Reset Value: 0x00000000
Bits | Field Name | RW | Reset | Description |
---|---|---|---|---|
31:24 |
RSVD |
R |
Reserved bits |
|
23:16 |
MSIO_A_VAL |
R |
0x0 |
MSIOA digital value |
15:8 |
MSIO_A_OE_N |
RW |
0xFF |
MSIOA output enable (active low) Value:
|
7:0 |
MSIO_A_OUT |
RW |
0x0 |
MSIOA output value (valid in output mode) |
MSIO_A_PAD_CFG1
- Name: MSIOA Pad Control Register
- Description: This register contains the MSIOA configurations.
- Base Address: 0x 4000A1DC
- Offset: 0x00
- Reset Value: 0x00FF0000
Bits | Field Name | RW | Reset | Description |
---|---|---|---|---|
31:24 |
MSIO_A_IE_N |
RW |
0x0 |
MSIOA input enable (active low) Value:
|
23:16 |
MSIO_A_RE_N |
RW |
0xFF |
MSIOA resistor enable (active low) Value:
|
15:8 |
MSIO_A_RTYPE |
RW |
0x0 |
MSIOA resistor type Value:
|
7:0 |
MSIO_A_AE_N |
RW |
0x0 |
Analog enable control for MSIOA pad Value:
|
MSIO_A_PAD_MCU_OVR
- Name: MSIOA Using MCU Domain Setting Control Register
- Description: This register controls MSIOA using the settings from the MCU domain.
- Base Address: 0x4000A1E0
- Offset: 0x0
- Reset Value: 0x00000000
Bits | Field Name | RW | Reset | Description |
---|---|---|---|---|
31:8 |
RSVD |
R |
N/A |
Reserved bits |
7:0 |
msio_a_mcu_ovr |
RW |
0x0 |
Use the settings from MCU domain, only valid when MCU domain is ON Value:
|
Electrical Specifications
The electrical parameters for the MSIO_A0–MSIO_A7 are as follows:
Parameter | Description | Min. | Typ. | Max. | Unit |
---|---|---|---|---|---|
VIH |
Input high voltage |
VDDIO x 0.7 |
VDDIO |
V |
|
VIL |
Input low voltage |
VSSIO |
VDDIO x 0.3 |
V |
|
VOH,L |
Output high voltage, 2.5 mA, VDDIO ≥ 1.7 V |
VDDIO – 0.4 |
VDDIO |
V |
|
VOH,M |
Output high voltage, 2.5 mA, VDDIO ≥ 2.5 V |
VDDIO – 0.4 |
VDDIO |
V |
|
VOH,H |
Output high voltage, 2.5 mA, VDDIO ≥ 3 V |
VDDIO – 0.4 |
VDDIO |
V |
|
VOL,L |
Output low voltage, 2.5 mA, VDDIO ≥ 1.7 V |
VSS |
VSS + 0.4 |
V |
|
VOL,M |
Output low voltage, 2.5 mA, VDDIO ≥ 2.5 V |
VSS |
VSS + 0.4 |
V |
|
VOL,H |
Output low voltage, 2.5 mA, VDDIO ≥ 3 V |
VSS |
VSS + 0.4 |
V |
|
IOL,L |
Current at VSS+0.4 V, output set low, VDDIO ≥1.7 V |
2.5 |
mA |
||
IOL,M |
Current at VSS+0.4 V, output set low, VDDIO ≥ 2.5 V |
2.5 |
mA |
||
IOH,L |
Current at VDD-0.4 V, output set high, VDDIO ≥ 1.7 V |
2.5 |
mA |
||
IOH,M |
Current at VDD-0.4 V, output set high, VDDIO ≥ 2.5 V |
2.5 |
mA |
||
tRF,15pF |
Rise/Fall time, 10%–90%, 15 pF load |
5 |
8 |
ns |
|
tRF,25pF |
Rise/Fall time, 10%–90%, 25 pF load |
6 |
13 |
ns |
|
RPU |
Pull-up resistance |
70 |
120 |
150 |
kΩ |
RPD |
Pull-down resistance |
70 |
120 |
150 |
kΩ |
CPAD |
Pad capacitance |
5 |
pF |