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Timer

Introduction

The GR5526 SoC has two instances of Timer module that is a 32-bit general-purpose timer. Since the Timer is in the MCU Subsystem domain, Timer interrupt is not available during sleep, and the running Timer will not prevent MCU from sleeping. In active mode, when Timer is started again after stopping, it will continue to count down from the stop time. The value of RELOAD register will not take effect until the end of the current cycle.

Main Features

  • Generate an interrupt when the 32-bit down counter reaches 0.
  • The clock source of the Timer follows the system clock.
  • Each timer module has an independent interrupt entry.
  • Timer pauses when MCU is suspended.

Functional Description

  • The Timer can generate an interrupt request signal when the 32-bit down counter reaches 0. The interrupt request is held until it is cleared by writing 1 to the INT_STAT register.
  • If the Timer count reaches 0 and, at the same time, the software clears a previous interrupt status, the interrupt status is set to 1.
  • When the value of the RELOAD register is configured to 0, no count and no interrupt are generated.
  • The RELOAD value only represents the count-down number of timers. If you want to configure a specific duration (for example, µs, ms, or s), you need to use the following formula:
    Expect_times=RELOAD/(SystemCoreClock-1)
  • If you need to start counting from the new RELOAD value immediately, you need to deinitialize the Timer first, and then initialize the Timer.

Registers

CTRL

  • Name: Timer Control Register
  • Description: The CTRL register enables the software to control the Timer.
  • Base Address: 0x40000000 + x*0x1000
  • Offset: 0x00
  • Reset Value: 0x00
Note:

*x is used to identify the Timer Module. The “x” can be 0 or 1.

表 175 CTRL Register
Bits Field Name RW Reset Description

31:4

RSVD

R

Reserved bits

3

INT_EN

RW

0x0

Timer interrupt enable

Value:

  • 0x0: Disable the Timer interrupt.
  • 0x1: Enable the Timer interrupt.

2:1

RSVD

R

Reserved bits

0

EN

RW

0x0

Timer enable.

Value:

  • 0x0: Disable the Timer.
  • 0x1: Enable the Timer.

VAL

  • Name: Timer Value Register
  • Description: The VAL register indicates the current value of the decrementing counter.
  • Base Address: 0x40000000 + x*0x1000
  • Offset: 0x04
  • Reset Value: 0x01
表 176 VAL Register
Bits Field Name RW Reset Description

31:0

CUR_VALUE

RW

0x1

Current value

RELOAD

  • Name: Timer Reload Register
  • Description: When this register is written to, the count value takes effect at the end of the current cycle.
  • Base Address: 0x40000000 + x*0x1000
  • Offset: 0x08
  • Reset Value: 0x00
表 177 RELOAD Register
Bits Field Name RW Reset Description

31:0

RELOAD_VALUE

RW

0x0

Sets reload value.

INT_STAT

  • Name: Timer Interrupt Status Register
  • Description: The INT_STAT register indicates the interrupt status from the counter. Writing one to the INT_STAT register clears the timer interrupt.
  • Base Address: 0x40000000 + x*0x1000
  • Offset: 0x0C
  • Reset Value: 0x00000000
表 178 INT_STAT Register
Bits Field Name RW Reset Description

31:1

RSVD

R

Reserved bits

0

STAT

RW

0x0

Timer interrupt. Write 1 to clear.

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