Hash-based Message Authentication Code (HMAC)

表 662 HMAC module standard

Document Code	Name of Standard
FIPS PUB 180-4	Secure Hash Standard (SHS) (Compliant with SHA-256)
FIPS PUB 198-1	Keyed-Hash Message Authentication Code (HMAC)

The HMAC co-processor authenticates data, using an algorithm and implementation fully compliant with the Keyed-Hash Message Authentication Code defined in Federal Information Processing Standards (FIPS) Publication 198. GR5526 embeds the HMAC module in order to realize hardware acceleration of calculation.

Multiple modes are supported (SHA256, HMAC-SHA256) for a key size of 256 bits.

Information preprocessing is required for input data, including additional padding bits and additional length value.

The HMAC co-processor adopts both 32-bit AHB and APB interfaces. It supports DMA transfers for incoming and outgoing data (through a dedicated integrated DMA).

The CFG register can be used to configure relevant parameters for the HMAC module. CFG.CALC_TYPE can be used to configure the working mode including SHA-256 and HMAC. If the working mode is set to HMAC, the mode of fetching the key should be configured through CFG.KEY_TYPE.

If the key is configured by MCU, the KEY0 to KEY7 registers need to be configured. If the key is fetched through AHB, the KEY_ADDR register should be configured.

The SER_HASH0 to USER_HASH7 registers are used to customize the initial HASH values if the CFG register enables users to define the initial HASH.

If the HMAC module is in interrupt or DMA operation mode, the INT register needs to be configured.

In DMA operation mode, the XFER_SIZE, RD_START_ADDR, and WR_START_ADDR registers should be configured. If misalignment is required when MCU reads or writes data, the last two bits of the RD_START_ADDR and the WR_START_ADDR registers can be configured.

The HMAC module can be started through the CTRL register. CTRL.KEY_EN is configured in order to enable the HMAC module to fetch the key through AHB master interface.

In MCU operation mode, a block data (512-bit) is continuously written into the DATA_IN register. In DMA operation mode, the HMAC module will read the data from the address which is stored in the RD_START_ADDR register.

The STAT register or interrupt callback function can judge whether the calculation completes. Before writing next block data into the DATA_IN register, the INT register needs to be cleared.

In MCU operation mode, the result of the SHA-256 or HMAC can be obtained by repeatedly reading the DATA_OUT register until getting 256-bit data. In DMA operation mode, the result has been sent to the address which is stored in the WR_START_ADDR register.

• Name: HMAC Controller Register
• Description: This register acts as a global enable/disable for HMAC.
• Base Address: 0x40015800
• Offset: 0x0
• Reset Value: 0x00000000

表 663 HMAC Controller Register

Bits	Field Name	RW	Reset	Description
31:4	RSVD	R		Reserved bits
3	LST_TX	W	0x0	Last block in MCU mode or last DMA transfer. This signal may be cleared by itself when hmac_ready was set.
2	KEY_EN	W	0x0	Enable HMAC fetch key by itself through AHB master interface or key port. This signal may be cleared by itself when hmac_key_valid was set.
1	DMA_START	RW	0x0	DMA mode start enable. Starting DMA transfer, this signal should be cleared after DMA has finished all transfers.
0	EN	RW	0x0	HMAC enable, high valid for whole HMAC processing. Users must disable it once all HMAC blocks complete. This signal should be asserted until all blocks complete.

• Name: HMAC Configuration Register
• Description: This register acts as a configuration for HMAC.
• Base Address: 0x40015800
• Offset: 0x4
• Reset Value: 0x00000000

表 664 HMAC Configuration Register

Bits	Field Name	RW	Reset	Description
31:6	RSVD	R		Reserved bits
5	PRIVT_MOD	RW	0x0	To resist DPA, select private mode. Value: 0x0: Standard mode 0x1: Private mode
4	CALC_TYPE	RW	0x0	Selects a calculation type. Value: 0x0: HMAC 0x1: SHA
3:2	KEY_TYPE	RW	0x0	Selects a key type. Value: 0x0: Configured by MCU 0x1: Fetched through AHB interface 0x2: Fetched through key port 0x3: Reserved
1	ENDIAN	RW	0x0	Selection for endian control Value: 0x0: Reverse to big-endian (default) 0x1: No reverse
0	HASH	RW	0x0	Enables user-defined hash. Value: 0x0: Initial Hash from standard (default) 0x1: User-defined initial Hash enabled

• Name: HMAC Status Register
• Description: This is a read-only register used to indicate the current status of HMAC.
• Base Address: 0x40015800
• Offset: 0x8
• Reset Value: 0x00000000

表 665 HMAC Status Register

Bits	Field Name	RW	Reset	Description
31:6	RSVD	R		Reserved bits
5	DMA_TX_DONE	R	0x0	HMAC DMA transfer done or not
4	HMAC_READY	R	0x0	HMAC process status Value: 0x0: Result data is not ready. 0x1: Result data is valid.
3	KEY_VALID	R	0x0	HMAC has fetched key or not
2	DMA_TX_ERR	R WC	0x0	HMAC DMA transfer error. Write 1 to clear.
1	DMA_MSG_DONE	R	0x0	If the number of all block messages is bigger than the transfer size, it indicates all block messages are sent when this signal is set.
0	HASH_READY	R	0x0	Hash process status Value: 0x0: Result data is not ready. 0x1: Result data is valid.

• Name: HMAC Transfer Size Register
• Description: This register sets a size for HMAC DMA mode transfer.
• Base Address: 0x40015800
• Offset: 0xC
• Reset Value: 0x00000000

表 666 HMAC Transfer Size Register

Bits	Field Name	RW	Reset	Description
31:15	RSVD	R		Reserved bits
14:0	SIZE	RW	0x0	Total transfer size. Up to 32 KB 0x003F: 1 block 0x007F: 2 blocks 0x00BF: 3 blocks … 0x7FFF: 512 blocks

• Name: HMAC Interrupt Register
• Description: This register enables or disables all interrupts generated by the HMAC. Additionally, it reports the status of the HMAC interrupts after they have been enabled.
• Base Address: 0x40015800
• Offset: 0x10
• Reset Value: 0x00000000

表 667 HMAC Interrupt Register

Bits	Field Name	RW	Reset	Description
31:2	RSVD	R		Reserved bits
1	EN	RW	0x0	HMAC result data complete interrupt Value: 0x0: Disable 0x1: Enable
0	DONE	R WC	0x0	HMAC result data complete interrupt flag. Write 1 to clear. Read: 0x0: Not interrupt 0x1: Interrupt Write: 0x0: Not effect 0x1: Clear

• Name: HMAC Read Start Address Register
• Description: This register acts as a start address for HMAC DMA reading.
• Base Address: 0x40015800
• Offset: 0x14
• Reset Value: 0x00000000

表 668 HMAC Read Start Address Register

Bits	Field Name	RW	Reset	Description
31:0	ADDR	RW	0x0	In DMA mode, set the read start address of transfer.

• Name: HMAC Write Start Address Register
• Description: This register acts as a start address for HMAC DMA writing.
• Base Address: 0x40015800
• Offset: 0x18
• Reset Value: 0x00000000

表 669 HMAC Write Start Address Register

Bits	Field Name	RW	Reset	Description
31:0	ADDR	RW	0x0	In DMA mode, set the write start address of transfer.

• Name: HMAC User Hash 0 Register
• Description: This register acts as a user Hash value for HASH calculation.
• Base Address: 0x40015800
• Offset: 0x20
• Reset Value: 0x00000000

表 670 HMAC User Hash 0 Register

Bits	Field Name	RW	Reset	Description
Bits	Field Name	RW	Reset	Description
31:0	HASH_0	RW	0x0	If UHASH is selected, you can configure a user-defined Hash value by using USER_HASH_0/1/2/3/4/5/6/7. User defined Hash value[255:224]

• Name: HMAC User Hash 1 Register
• Description: This register acts as a user Hash value for HASH calculation.
• Base Address: 0x40015800
• Offset: 0x24
• Reset Value: 0x00000000

表 671 HMAC User Hash 1 Register

Bits	Field Name	RW	Reset	Description
31:0	HASH_1	RW	0x0	If UHASH is selected, you can configure a user-defined Hash value by using USER_HASH_0/1/2/3/4/5/6/7. User defined Hash value[223:192]

• Name: HMAC User Hash 2 Register
• Description: This register acts as a user Hash value for HASH calculation.
• Base Address: 0x40015800
• Offset: 0x28
• Reset Value: 0x00000000

表 672 HMAC User Hash 2 Register

Bits	Field Name	RW	Reset	Description
31:0	HASH_2	RW	0x0	If UHASH is selected, you can configure a user-defined Hash value by using USER_HASH_0/1/2/3/4/5/6/7. User defined Hash value[191:160]

• Name: HMAC User Hash 3 Register
• Description: This register acts as a user Hash value for HASH calculation.
• Base Address: 0x40015800
• Offset: 0x2C
• Reset Value: 0x00000000

表 673 HMAC User Hash 3 Register

Bits	Field Name	RW	Reset	Description
31:0	HASH_3	RW	0x0	If UHASH is selected, you can configure a user-defined Hash value by using USER_HASH_0/1/2/3/4/5/6/7. User defined Hash value[159:128]

• Name: HMAC User Hash 4 Register
• Description: This register acts as a user Hash value for HASH calculation
• Base Address: 0x40015800
• Offset: 0x30
• Reset Value: 0x00000000

表 674 HMAC User Hash 4 Register

Bits	Field Name	RW	Reset	Description
31:0	HASH_4	RW	0x0	If UHASH is selected, you can configure a user-defined Hash value with USER_HASH_0/1/2/3/4/5/6/7. User defined Hash value[127:96]

• Name: HMAC User Hash 5 Register
• Description: This register acts as a user Hash value for HASH calculation.
• Base Address: 0x40015800
• Offset: 0x34
• Reset Value: 0x00000000

表 675 HMAC User Hash 5 Register

Bits	Field Name	RW	Reset	Description
31:0	HASH_5	RW	0x0	If UHASH is selected, you can configure a user-defined Hash value by using USER_HASH_0/1/2/3/4/5/6/7. User defined Hash value[95:64]

• Name: HMAC User Hash 6 Register
• Description: This register acts as a user Hash value for HASH calculation.
• Base Address: 0x40015800
• Offset: 0x38
• Reset Value: 0x00000000

表 676 HMAC User Hash 6 Register

Bits	Field Name	RW	Reset	Description
31:0	HASH_6	RW	0x0	If UHASH is selected, you can configure a user-defined Hash value by using USER_HASH_0/1/2/3/4/5/6/7. User defined Hash value[63:32]

• Name: HMAC User Hash 7 Register
• Description: This register acts as a user Hash value for HASH calculation.
• Base Address: 0x40015800
• Offset: 0x3C
• Reset Value: 0x00000000

表 677 HMAC User Hash 7 Register

Bits	Field Name	RW	Reset	Description
31:0	HASH_7	RW	0x0	If UHASH is selected, you can configure a user-defined Hash value by using USER_HASH_0/1/2/3/4/5/6/7. User defined Hash value[31:0]

• Name: HMAC Data Output Register
• Description: This register is a 32-bit only read buffer for the result data from HMAC.
• Base Address: 0x40015800
• Offset: 0x40
• Reset Value: 0x00000000

表 678 HMAC Data Output Register

Bits	Field Name	RW	Reset	Description
31:0	DATA	R	0x0	In MCU mode, users can read out results with this register: When all blocks of messages are processed, 256-bit HMAC data should be read out 8 or 9 times. HMAC data can be read when hmac_ready is valid.

• Name: HMAC Data Input Register
• Description: This register is a 32-bit only write buffer for the input data for HMAC.
• Base Address: 0x40015800
• Offset: 0x44
• Reset Value: 0x00000000

表 679 HMAC Data Input Register

Bits	Field Name	RW	Reset	Description
Bits	Field Name	RW	Reset	Description
31:0	DATA	W	0x0	In MCU mode, users can configure input data with this register: 32-bit data should be sent 16 or 17 times.

• Name: HMAC Key 0 Register
• Description: This register is a 32-bit only write buffer for the key data[255:224] for HMAC.
• Base Address: 0x40015800
• Offset: 0x48
• Reset Value: 0x00000000

表 680 HMAC Key 0 Register

Bits	Field Name	RW	Reset	Description
31:0	KEY0	W	0x0	Key is set as 256 bits (8 words). WORD0

• Name: HMAC Key 1 Register
• Description: This register is a 32-bit only write buffer for the key data[223:192] for HMAC.
• Base Address: 0x40015800
• Offset: 0x4C
• Reset Value: 0x00000000

表 681 HMAC Key 1 Register

Bits	Field Name	RW	Reset	Description
31:0	KEY1	W	0x0	Key is set as 256 bits (8 words). WORD1

• Name: HMAC Key 2 Register
• Description: This register is a 32-bit only write buffer for the key data[191:160] for HMAC.
• Base Address: 0x40015800
• Offset: 0x50
• Reset Value: 0x00000000

表 682 HMAC Key 2 Register

Bits	Field Name	RW	Reset	Description
31:0	KEY2	W	0x0	Key is set as 256 bits (8 words). WORD2

• Name: HMAC Key 3 Register
• Description: This register is a 32-bit only write buffer for the key data[159:128] for HMAC.
• Base Address: 0x40015800
• Offset: 0x54
• Reset Value: 0x00000000

表 683 HMAC Key 3 Register

Bits	Field Name	RW	Reset	Description
31:0	KEY3	W	0x0	Key is set as 256 bits (8 words). WORD3

• Name: HMAC Key 4 Register
• Description: This register is a 32-bit only write buffer for the key data[127:96] for HMAC.
• Base Address: 0x40015800
• Offset: 0x58
• Reset Value: 0x00000000

表 684 HMAC Key 4 Register

Bits	Field Name	RW	Reset	Description
31:0	KEY4	W	0x0	Key is set as 256 bits (8 words). WORD4

• Name: HMAC Key 5 Register
• Description: This register is a 32-bit only write buffer for the key data[95:64] for HMAC.
• Base Address: 0x40015800
• Offset: 0x5C
• Reset Value: 0x00000000

表 685 HMAC Key 5 Register

Bits	Field Name	RW	Reset	Description
31:0	KEY5	W	0x0	Key is set as 256 bits (8 words). WORD5

• Name: HMAC Key 6 Register
• Description: This register is a 32-bit only write buffer for the key data[63:32] for HMAC.
• Base Address: 0x40015800
• Offset: 0x60
• Reset Value: 0x00000000

表 686 HMAC Key 6 Register

Bits	Field Name	RW	Reset	Description
Bits	Field Name	RW	Reset	Description
31:0	KEY6	W	0x0	Key is set as 256 bits (8 words). WORD6

• Name: HMAC Key 7 Register
• Description: This register is a 32-bit only write buffer for the key data[31:0] for HMAC.
• Base Address: 0x40015800
• Offset: 0x64
• Reset Value: 0x00000000

表 687 HMAC Key 7 Register

Bits	Field Name	RW	Reset	Description
31:0	KEY7	W	0x0	Key is set as 256 bits (8 words). WORD7

• Name: HMAC Key Address Register
• Description: This register acts as a key address for HMAC.
• Base Address: 0x40015800
• Offset: 0x68
• Reset Value: 0x00000000

表 688 HMAC Key Address Register

Bits	Field Name	RW	Reset	Description
31:0	KEY_ADDR	RW	0x0	Indicates the HMAC key address in memory.

• Name: HMAC Keyport Mask Register
• Description: This register acts as a mask for key from key port.
• Base Address: 0x40015800
• Offset: 0x6C
• Reset Value: 0x00000000

表 689 HMAC Keyport Mask Register

Bits	Field Name	RW	Reset	Description
31:0	MASK	W	0x0	Mask for key from key port