GPU

The fixed-point data path and instruction set architecture (ISA) of the GPU are tailored specifically for GUIs acceleration and small display applications, resulting in significant improvements in power consumption and silicon area. The GPU combines hardware-level support for multithreading, VLIW, and low-level vector processing in the most energy-efficient way. The GPU block diagram is shown above.

The GPU supports connection via AHB that helps it communicate with the MCU, configuration registers, and system memory. The GPU uses two 32-bit AHB master ports that enable access to the main memory and that support data fetch from the G PU (such as textures and frame data). The AHB version of the system fetches both the command lists and rendering data over the same read bus.

The GPU is programmed through a set of registers which are known as configuration register file (CRF), and each sub-module of the GPU is programmed through a subset of the CRF. CRF can be memory-mapped to the CPU address space, making it directly accessible. Writing CRF directly is considered inefficient because it consumes a lot of CPU resources and associates CPU execution with the GPU. Therefore, the GPU supports indirect CRF access through the Command List Processor (CLP).

In order to decouple CPU from GPU execution and achieve both better performance and lower power consumption, the GPU incorporates an advanced Command List Processor (CLP), capable of reading entire lists of commands from the main memory and relaying them to the CRF.

The CPU pre-assembles Command Lists (CLs) prior to submitting them to the CLP for execution, while a single CL can be submitted multiple times. This approach alleviates the CPU from recalculating drawing operations for repetitive tasks, resulting in more efficient resource utilization.

The steps for writing commands to the configuration registers through the CLP are the following:

1. The CPU assembles a CL, through the GFX library.
2. The CPU submits the CL for execution. The CLP is informed of a pending CL.
3. The CLP reads the CL from the system memory.
4. The CLP relays the commands to the Configuration Register File.

The GPU can draw a multitude of geometrical shapes called Geometric Primitives, such as lines, rectangles, triangles, and quadrilaterals. The rasterizer unit reads the coordinates of the primitives’ vertices and feeds the rest of the graphics pipeline with the fragments contained in the geometry. A fragment contains information concerning a single pixel. This information includes raster position (coordinates), texture coordinates, interpolated color, and alpha values.

The rasterizer can draw:

• Line drawing (at any direction)
• Filled rectangles
• Quadrilaterals
• Triangles

In addition, the rasterizer handles clipping by either dropping fragments that are outside the effective drawing area and back-face culling or dropping entire primitives that are considered to be non-visible, like the rear looking faces of a cube. If a pixel resides inside or outside of the geometry primitive, the pixel is determined by the value of E which is positive inside the geometry primitive and negative outside of it.

The pixel’s edge function value is calculated for each line of the geometry primitive (for example, 3 times for a triangle) using the following equation:

Although the equation requires two multiplications and two additions since the variation is always one pixel on the X or Y axis, this is reduced to a single accumulator.

The color variances are also calculated in a similar way, where each of the RGBA components is linearly interpolated across the geometry of the primitive. If H/W Blender is enabled, each edge can be independently programmed to either have antialiasing or not. The rasterizer also determines the coverage value of each pixel as a function of the pixel center to the closest edge distance.

Transformations are performed using matrix multiplication. The Vector Matrix Multiplier multiplies a 2 x 1 Vector (x,y) by a 3 x 3 homogeneous Matrix to produce a new 2 x 1 Vector (Tx,Ty). The following computation is required to calculate texel coordinates from screen coordinates:

The texture map unit produces texels that are sent to the fragment processing core. It is fed with texture’s attributes (base address, dimensions, color format) and the required coordinates. The texture map unit performs some internal processing and outputs the corresponding texel. Generating a texture element requires a series of operations like wrapping (clamp, mirror, and repeat), reading corresponding color values from memory, converting the color values to RGBA8888 format, and performing filtering if necessary.

The fragment processing core is the main processing unit of the GPU’s architecture. It is a 64-bit VLIW processor which performs computations on the fragments coming from the rasterizer unit and on the texels coming from the texture map unit and calculates the final color to a fragment. The core is programmable through binary executables called Fragment Shaders.

The render output unit (ROP) is the last stage of the graphics pipeline. The fragment processing core feeds the ROP with the pixel’s coordinates and color value. Before the color value is written to the memory, the color is converted to the frambuffer’s format.

If H/W Blender is enabled, the ROP reads pixels from the fragment processing core (source) and pixels from the framebuffer (destination) to perform blending. Blending requires a series of calculations between the source (foreground) and destination (background) color fragments to produce the final color, which is written back to memory. The following equations are used for the final color:

• F_c: Final Color
• S_c: Source Color
• S_f: Source Blend Factor (multiplier)
• D_c: Destination Color
• D_f: Destination Blend Factor (multiplier)
• F_a: Final Alpha
• S_a: Source Alpha
• D_a: Destination Alpha

The Color and Alpha values range from 0 to 1, therefore each calculation result is also clamped to the same range. The available Blend Factors and the resulting RGBA values are listed in the table below. The effect of the blending modes is shown in the figure below.

表 465 Blend factors

Blending Mode Name	Blend Factors (Sc or Df )	RGBA Value	Definition
DSBF_ZERO	0	0,0,0,0
DSBF_ONE	1	1,1,1,1
DSBF_SRCCOLOR	Sc	Rsrc, Gsrc, Bsrc, Asrc	Sc: Source Color Rsrc: Source Red value Gsrc: Source Green value Bsrc: Source Blue value Asrc: Source Alpha value
DSBF_INVSRCCOLOR	(1 – Sc)	1 – Rsrc, 1 – Gsrc, 1–Bsrc, 1 – Asrc
DSBF_SRCALPHA	Sa	Asrc, Asrc, Asrc, Asrc	Sa: Source Alpha Asrc: Source Alpha value
DSBF_INVSRCALPHA	(1 – Sa)	1 – Asrc, 1 – Asrc, 1 – Asrc, 1 – Asrc
DSBF_DESTALPHA	Da	Adst, Adst, Adst, Adst	Da: Destination Alpha Adst: Destination Alpha value
DSBF_INVDESTALPHA	(1 – Da)	1 – Adst, 1 – Adst, 1 – Adst, 1 – Adst
DSBF_DESTCOLOR	Dc	Rdst, Gdst, Bdst, Adst	Dc: Destination Color Rdst: Destination Red value Gdst: Destination Green value Bdst: Destination Blue value Adst: Destination Alpha value
DSBF_INVDESTCOLOR	(1 – Dc)	1 – Rdst, 1 – Gdst, 1 – Bdst, 1 – Adst
DSBF_CONSTCOLOR	Cc	Rconst, Gconst, Bconst, Aconst	Cc: Constant Color Ca: Constant Alpha Rconst: Constant Red value Gconst: Constant Green value Bconst: Constant Blue value Aconst: Constant Alpha value
DSBF_CONSTALPHA	Ca	Aconst, Aconst, Aconst, Aconst
DSBF_UNKNOWN	0	0,0,0,0

Framebuffer compression operates in screen blocks (4 x 4 pixel blocks) and achieves TSC^TM4, TSC^TM6 and TSC^TM6a lossy, fixed-ratio compression depending on the configuration.

• TSC^TM4 is a 6:1 compression (4bpp).
• TSC^TM6 is a 4:1 compression (6bpp).
• TSC^TM6a is a 4:1 compression (6bpp) with alpha channel.

Compression is performed at run time using minimal hardware. Pixel data can be stored in the framebuffer in compressed form and decompressed in the display control (DC) module. The output of the TSC^TM4 compression is 64 bits per 4 x 4 block of pixels, and the output of the TSC^TM6 compression is 96 bits per 4 x 4 block of pixels.

The GPU supports multiple color formats. The supported color formats are the following:

• RGBX8888 32-bit

表 466 RGBX8888 32-bit

Pixel 0
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
X7	X6	X5	X4	X3	X2	X1	X0	B7	B6	B5	B4	B3	B2	B1	B0	G7	G6	G5	G4	G3	G2	G1	G1	R7	R6	R5	R4	R3	R2	R1	R0
Byte 3								Byte 2								Byte 1								Byte 0

• RGBA8888 32-bit

表 467 RGBA8888 32-bit

Pixel 0
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
A7	A6	A5	A4	A3	A2	A1	A0	B7	B6	B5	B4	B3	B2	B1	B0	G7	G6	G5	G4	G3	G2	G1	G1	R7	R6	R5	R4	R3	R2	R1	R0
Byte 3								Byte 2								Byte 1								Byte 0

• XRGB8888 32-bit

表 468 XRGB8888 32-bit

Pixel 0
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
B7	B6	B5	B4	B3	B2	B1	B0	G7	G6	G5	G4	G3	G2	G1	G1	R7	R6	R5	R4	R3	R2	R1	R0	X7	X6	X5	X4	X3	X2	X1	X0
Byte 3								Byte 2								Byte 1								Byte 0

• ARGB8888 32-bit

表 469 ARGB8888 32-bit

Pixel 0
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
B7	B6	B5	B4	B3	B2	B1	B0	G7	G6	G5	G4	G3	G2	G1	G1	R7	R6	R5	R4	R3	R2	R1	R0	A7	A6	A5	A4	A3	A2	A1	A0
Byte 3								Byte 2								Byte 1								Byte 0

• RGB5650 16-bit

表 470 RGB5650 16-bit

Pixel 0
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
R4	R3	R2	R1	R0	G5	G4	G3	G2	G1	G1	B4	B3	B2	B1	B0
Byte 1								Byte 0

• RGBA5551 16-bit

表 471 RGBA5551 16-bit

Pixel 0
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
R4	R3	R2	R1	R0	G4	G3	G2	G1	G1	B4	B3	B2	B1	B0	A0
Byte 1								Byte 0

• RGBA4444 16-bit

表 472 RGBA4444 16-bit

Pixel 0
15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
R3	R2	R1	R0	G3	G2	G1	G1	B3	B2	B1	B0	A3	A2	A1	A0
Byte 1								Byte 0

• RGBA0008 8-bit

表 473 RGBA0008 8-bit

Pixel 0
7	6	5	4	3	2	1	0
A7	A6	A5	A4	A3	A2	A1	A0
Byte 0

• L8 8-bit

表 474 L8 8-bit

Pixel 0
7	6	5	4	3	2	1	0
L7	L6	L5	L4	L3	L2	L1	L0
Byte 0

• L1 big-endian 1-bit

表 475 L1 big-endian 1-bit

Pixel 0	Pixel 1	Pixel 2	Pixel 3	Pixel 4	Pixel 5	Pixel 6	Pixel 7
7	6	5	4	3	2	1	0
L0	L0	L0	L0	L0	L0	L0	L0
Byte 0

• A1 big-endian 1-bit

表 476 A1 big-endian 1-bit

Pixel 0	Pixel 1	Pixel 2	Pixel 3	Pixel 4	Pixel 5	Pixel 6	Pixel 7
7	6	5	4	3	2	1	0
A0	A0	A0	A0	A0	A0	A0	A0
Byte 0

• UYVY 32-bit 2-pixel

表 477 UYVY 32-bit 2-pixel

Pixel 1								Pixel1&0								Pixel 0								Pixel1&0
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
Y7	Y6	Y5	Y4	Y3	Y2	Y1	Y0	V7	V6	V5	V4	V3	V2	V1	V0	Y7	Y6	Y5	Y4	Y3	Y2	Y1	Y1	U7	U6	U5	U4	U3	U2	U1	U0
Byte 3								Byte 2								Byte 1								Byte 0

• ABGR8888 32-bit

表 478 ABGR8888 32-bit

Pixel 0
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
R7	R6	R5	R4	R3	R2	R1	R0	G7	G6	G5	G4	G3	G2	G1	G1	B7	B6	B5	B4	B3	B2	B1	B0	A7	A6	A5	A4	A3	A2	A1	A0
Byte 3								Byte 2								Byte 1								Byte 0

• BGRA 32-bit

表 479 BGRA 32-bit

Pixel 0
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
A7	A6	A5	A4	A3	A2	A1	A0	R7	R6	R5	R4	R3	R2	R1	R0	G7	G6	G5	G4	G3	G2	G1	G1	B7	B6	B5	B4	B3	B2	B1	B0
Byte 3								Byte 2								Byte 1								Byte 0

• BGRX 32-bit

表 480 BGRX 32-bit

Pixel 0
31	30	29	28	27	26	25	24	23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
X7	X6	X5	X4	X3	X2	X1	X0	R7	R6	R5	R4	R3	R2	R1	R0	G7	G6	G5	G4	G3	G2	G1	G1	B7	B6	B5	B4	B3	B2	B1	B0
Byte 3								Byte 2								Byte 1								Byte 0

• TSC4 16-pixel/64-bit
• TSC6 16-pixel/96-bit
• TSC6A 16-pixel with Alpha/96-bit
• A1LE little-endian 1-bit

表 481 A1LE little-endian 1-bit

Pixel 7	Pixel 6	Pixel 5	Pixel 4	Pixel 3	Pixel 2	Pixel 1	Pixel 0
7	6	5	4	3	2	1	0
A0	A0	A0	A0	A0	A0	A0	A0
Byte 0

• A2LE little-endian 2-bit

表 482 A2LE little-endian 2-bit

Pixel 3		Pixel 2		Pixel 1		Pixel 0
7	6	5	4	3	2	1	0
A1	A0	A1	A0	A1	A0	A1	A0
Byte 0

• A4LE little-endian 4-bit

表 483 A4LE little-endian 4-bit

Pixel 1				Pixel 0
7	6	5	4	3	2	1	0
A3	A2	A1	A0	A3	A2	A1	A0
Byte 0

• L1LE little-endian 1-bit

表 484 L1LE little-endian 1-bit

Pixel 7	Pixel 6	Pixel 5	Pixel 4	Pixel 3	Pixel 2	Pixel 1	Pixel 0
7	6	5	4	3	2	1	0
L0	L0	L0	L0	L0	L0	L0	L0
Byte 0

• L2LE little-endian 2-bit

表 485 L2LE little-endian 2-bit

Pixel 3		Pixel 2		Pixel 1		Pixel 0
7	6	5	4	3	2	1	0
L1	L0	L1	L0	L1	L0	L1	L0
Byte 0

• L4LE little-endian 4-bit

表 486 L4LE little-endian 4-bit

Pixel 1				Pixel 0
7	6	5	4	3	2	1	0
L3	L2	L1	L0	L3	L2	L1	L0
Byte 0

• A2 big-endian 2-bit

表 487 A2 big-endian 2-bit

Pixel 0		Pixel 1		Pixel 2		Pixel 3
7	6	5	4	3	2	1	0
A1	A0	A1	A0	A1	A0	A1	A0
Byte 0

• L2 big-endian 2-bit

表 488 L2 big-endian 2-bit

Pixel 0		Pixel 1		Pixel 2		Pixel 3
7	6	5	4	3	2	1	0
L1	L0	L1	L0	L1	L0	L1	L0
Byte 0

• A4 big-endian 4-bit

表 489 A4 big-endian 4-bit

Pixel 0				Pixel 1
7	6	5	4	3	2	1	0
A3	A2	A1	A0	A3	A2	A1	A0
Byte 0

• L4 big-endian 4-bit

表 490 L4 big-endian 4-bit

Pixel 0				Pixel 1
7	6	5	4	3	2	1	0
L3	L2	L1	L0	L3	L2	L1	L0
Byte 0

• RGBA3320 8-bit

表 491 RGBA3320 8-bit

Pixel 0
7	6	5	4	3	2	1	0
R2	R1	R0	G2	G1	G0	B1	B0
Byte 0

• BGR24 24-bit

表 492 BGR24 24-bit

Pixel 0
23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
R7	R6	R5	R4	R3	R2	R1	R0	G7	G6	G5	G4	G3	G2	G1	G0	B7	B6	B5	B4	B3	B2	B1	B0
Byte 2								Byte 1								Byte 0

• RGB24 24-bit

表 493 RGB24 24-bit

Pixel 0
23	22	21	20	19	18	17	16	15	14	13	12	11	10	9	8	7	6	5	4	3	2	1	0
B7	B6	B5	B4	B3	B2	B1	B0	G7	G6	G5	G4	G3	G2	G1	G0	R7	R6	R5	R4	R3	R2	R1	R0
Byte 2								Byte 1								Byte 0

The internal format is always on RGBA8888 32-bit format. Therefore, lower-order color formats are expanded to 8 bits per color channel. This is achieved by high-order bit replication. For example, a 5-bit color format is constructed as follows:

The microarchitecture of the GPU for fragment processing is a four-issue VLIW core. Each VLIW instruction is 64 bits’ long and consists of four sub-instructions (corresponding to sub-operations). The sub-operations for the GPU are: i) instructions for Alpha channel arithmetic operations (SUBOP0); ii) instructions for RGB vector arithmetic operations (SUBOP1); iii) memory addressing instructions for reading and writing to memory (SUBOP2); and iv) branching instructions based on comparisons between RGB or Alpha values (SUBOP3).

Each VLIW bundle is designed to perform six arithmetic operations per cycle (simultaneously). If more than one VLIW bundle is enabled, the addressing sub-operations (SUBOP2) are issued once for all the enabled bundles while the remaining sub-operations (SUBOP0, SUBOP1, and SUBOP3) are issued once for each VLIW bundle.

• Name: Base Address Register 0
• Description: This register specifies the base address of drawing surface 0.
• Base Address: 0x40028000
• Offset: 0x0
• Reset Value: 0x00000000

表 494 Base Address Register 0

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the base address of drawing surface 0.

• Name: Image Stride Register 0
• Description: This register specifies image 0 mode and stride.
• Base Address: 0x40028000
• Offset: 0x4
• Reset Value: 0x00000000

表 495 Image Stride Register 0

Bits	Field Name	RW	Reset	Description
31		RW	0x0	If set for destination texture, color dithering is enabled. (Applicable to output formats: RGBA5650, RGBA5551, and RGBA4444).
30:24		RW	0x0	Specifies the image format. 0x00: RGBX8888 0x01: RGBA8888 0x02: XRGB8888 0x03: ARGB8888 0x04: RGBA5650 0x05: RGBA555 0x06: RGBA44441 0x08: RGBA0008 (only available as input format) 0x09: L8 0x0B: L1 (only available as input format) 0x0C: A1 (only available as input format) 0x0D: UYVY (only available as input format) 0x0E: ABGR8888 (only available as input format) 0x10: BGRA (only available as input format) 0x11: BGRX (only available as input format) 0x12: TSC4 0x16: TSC6 0x17: TSC6A 0x27: A1LE (only available as input format) 0x28: A2LE (only available as input format) 0x29: A4LE (only available as input format) 0x2A: L1LE (only available as input format) 0x2B: L2LE (only available as input format) 0x2C: L4LE (only available as input format) 0x30: A2 (only available as input format) 0x31: L2 (only available as input format) 0x34: A4 (only available as input format) 0x35: L4 (only available as input format) 0x38: RGBA3320 (only available as input format) 0x39: BGR24 0x3C: RGB24
23:16		RW	0x0	Specifies the image mode. 0x00: Point sampling 0x01: Bilinear filtering
15:0		RW	0x0	Specifies the image stride distance in bytes from one scanline to another (signed).

• Name: Image Size Register 0
• Description: This register specifies the size of image 0 resolution.
• Base Address: 0x40028000
• Offset: 0x8
• Reset Value: 0x00000000

表 496 Image Size Register 0

Bits	Field Name	RW	Reset	Description
31:16		RW	0x0	Specifies the size of resolution Y.
15:0		RW	0x0	Specifies the size of resolution X.

• Name: Base Address Register 1
• Description: This register specifies the base address of drawing surface 1.
• Base Address: 0x40028000
• Offset: 0x10
• Reset Value: 0x00000000

表 497 Base Address Register 1

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the base address of drawing surface 1.

• Name: Image Stride Register 1
• Description: This register specifies image 1 mode and stride.
• Base Address: 0x40028000
• Offset: 0x14
• Reset Value: 0x00000000

表 498 Image Stride Register 1

Bits	Field Name	RW	Reset	Description
31		RW	0x0	If set for destination texture, enables color dithering. (Applicable to output formats: RGBA5650, RGBA5551, and RGBA4444).
30:24		RW	0x0	Specifies the image format. 0x00: RGBX8888 0x01: RGBA8888 0x02: XRGB8888 0x03: ARGB8888 0x04: RGBA5650 0x05: RGBA5551 0x06: RGBA4444 0x08: RGBA0008 (only available as input format) 0x09: L8 0x0B: L1 (only available as input format) 0x0C: A1 (only available as input format) 0x0D: UYVY (only available as input format) 0x0E: ABGR8888 (only available as input format) 0x10: BGRA (only available as input format) 0x11: BGRX (only available as input format) 0x12: TSC4 0x16: TSC6 0x17: TSC6A 0x27: A1LE (only available as input format) 0x28: A2LE (only available as input format) 0x29: A4LE (only available as input format) 0x2A: L1LE (only available as input format) 0x2B: L2LE (only available as input format) 0x2C: L4LE (only available as input format) 0x30: A2 (only available as input format) 0x31: L2 (only available as input format) 0x34: A4 (only available as input format) 0x35: L4 (only available as input format) 0x38: RGBA3320 (only available as input format) 0x39: BGR24 0x3C: RGB24
23:16		RW	0x0	Specifies the image mode. 0x00: Point sampling 0x01: Bilinear filtering
15:0		RW	0x0	Specifies the image stride distance in bytes from one scanline to another (signed).

• Name: Image Size Register 1
• Description: This register specifies the size of image 1 resolution.
• Base Address: 0x40028000
• Offset: 0x18
• Reset Value: 0x00000000

表 499 Image Size Register 1

Bits	Field Name	RW	Reset	Description
31:16		RW	0x0	Specifies the size of resolution Y.
15:0		RW	0x0	Specifies the size of resolution X.

• Name: Color Register
• Description: This register specifies texture map’s default color.
• Base Address: 0x40028000
• Offset: 0x1C
• Reset Value: 0x00000000

表 500 Color Register

Bits	Field Name	RW	Reset	Description
31:24		RW	0x0	Specifies the Alpha (A) value.
23:16		RW	0x0	Specifies the Blue (B) value.
15:8		RW	0x0	Specifies the Green (G) value.
7:0		RW	0x0	Specifies the Red (R) value.

• Name: Base Address Register 2
• Description: This register specifies the base address of drawing surface 2.
• Base Address: 0x40028000
• Offset: 0x20
• Reset Value: 0x00000000

表 501 Base Address Register 2

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the base address of drawing surface 2.

• Name: Image Stride Register 2
• Description: This register specifies image 2 mode and stride.
• Base Address: 0x40028000
• Offset: 0x24
• Reset Value: 0x00000000

表 502 Image Stride Register 2

Bits	Field Name	RW	Reset	Description
31		RW	0x0	If set for destination texture, color dithering is enabled. (Applicable to output formats: RGBA5650, RGBA5551, and RGBA4444).
30:24		RW	0x0	Specifies the image format. 0x00: RGBX8888 0x01: RGBA8888 0x02: XRGB8888 0x03: ARGB8888 0x04: RGBA5650 0x05: RGBA5551 0x06: RGBA4444 0x08: RGBA0008 (only available as input format) 0x09: L8 0x0B: L1 (only available as input format) 0x0C: A1 (only available as input format) 0x0D: UYVY (only available as input format) 0x0E: ABGR8888 (only available as input format) 0x10: BGRA (only available as input format) 0x11: BGRX (only available as input format) 0x12: TSC4 0x16: TSC6 0x17: TSC6A 0x27: A1LE (only available as input format) 0x28: A2LE (only available as input format) 0x29: A4LE (only available as input format) 0x2A: L1LE (only available as input format) 0x2B: L2LE (only available as input format) 0x2C: L4LE (only available as input format) 0x30: A2 (only available as input format) 0x31: L2 (only available as input format) 0x34: A4 (only available as input format) 0x35: L4 (only available as input format) 0x38: RGBA3320 (only available as input format) 0x39: BGR24 0x3C: RGB24
23:16		RW	0x0	Specifies the image mode. 0x00: Point sampling 0x01: Bilinear filtering
15:0		RW	0x0	Specifies the image stride distance in bytes from one scanline to another (signed).

• Name: Image Size Register 2
• Description: This register specifies the size of image 2 resolution.
• Base Address: 0x40028000
• Offset: 0x28
• Reset Value: 0x00000000

表 503 Image Size Register 2

Bits	Field Name	RW	Reset	Description
31:16		RW	0x0	Specifies the size of resolution Y.
15:0		RW	0x0	Specifies the size of resolution X.

• Name: Base Address Register 3
• Description: This register specifies the base address of drawing surface 3.
• Base Address: 0x40028000
• Offset: 0x30
• Reset Value: 0x00000000

表 504 Base Address Register 3

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the base address of drawing surface 3.

• Name: Image Stride Register 3
• Description: This register specifies image 3 mode and stride.
• Base Address: 0x40028000
• Offset: 0x34
• Reset Value: 0x00000000

表 505 Image Stride Register 3

Bits	Field Name	RW	Reset	Description
31		RW	0x0	If set for destination texture, color dithering is enabled. (Applicable to output formats: RGBA5650, RGBA5551, and RGBA4444).
30:24		RW	0x0	Specifies the image format. 0x00: RGBX8888 0x01: RGBA8888 0x02: XRGB8888 0x03: ARGB8888 0x04: RGBA5650 0x05: RGBA5551 0x06: RGBA4444 0x08: RGBA0008 (only available as input format) 0x09: L8 0x0B: L1 (only available as input format) 0x0C: A1 (only available as input format) 0x0D: UYVY (only available as input format) 0x0E: ABGR8888 (only available as input format) 0x10: BGRA (only available as input format) 0x11: BGRX (only available as input format) 0x12: TSC4 0x16: TSC6 0x17: TSC6A 0x27: A1LE (only available as input format) 0x28: A2LE (only available as input format) 0x29: A4LE (only available as input format) 0x2A: L1LE (only available as input format) 0x2B: L2LE (only available as input format) 0x2C: L4LE (only available as input format) 0x30: A2 (only available as input format) 0x31: L2 (only available as input format) 0x34: A4 (only available as input format) 0x35: L4 (only available as input format) 0x38: RGBA3320 (only available as input format) 0x39: BGR24 0x3C: RGB24
23:16		RW	0x0	Specifies the image mode. 0x00: Point sampling 0x01: Bilinear filtering
15:0		RW	0x0	Specifies the image stride distance in bytes from one scanline to another (signed).

• Name: Image Size Register 3
• Description: This register specifies the size of image 3 resolution.
• Base Address: 0x40028000
• Offset: 0x38
• Reset Value: 0x00000000

表 506 Image Size Register 3

Bits	Field Name	RW	Reset	Description
31:16		RW	0x0	Specifies the size of resolution Y.
15:0		RW	0x0	Specifies the size of resolution X.

• Name: Break Point Register
• Description: This register specifies the break point.
• Base Address: 0x40028000
• Offset: 0x80
• Reset Value: 0x00000000

表 507 Break Point Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0

• Name: Break Point Mask Register
• Description: This register specifies the break point mask.
• Base Address: 0x40028000
• Offset: 0x8C
• Reset Value: 0x00000000

表 508 Break Point Mask Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0

• Name: Clock Gating Control Register
• Description: This register controls the clock gating.
• Base Address: 0x40028000
• Offset: 0x94
• Reset Value: 0x00000000

表 509 Clock Gating Control Register

Bits	Field Name	RW	Reset	Description
31		RW	0x0	Disable clock gating for all modules.
30:28	RSVD	R		Reserved bits
27		RW	0x0	Disable clock gating for Core 0 Instruction Memory.
26:24	RSVD	R		Reserved bits
23		RW	0x0	Disable clock gating for Core 0.
22:20	RSVD	R		Reserved bits
19		RW	0x0	Disable clock gating for Core 0 Scheduler.
18:16	RSVD	R		Reserved bits
15		RW	0x0	Disable clock gating for Core 0 Register File.
14:12	RSVD	R		Reserved bits
11		RW	0x0	Disable clock gating for Core 0 Pipeline.
10:8	RSVD	R		Reserved bits
7		RW	0x0	Disable clock gating for the BusInterface (memory system).
6:4	RSVD	R		Reserved bits
3		RW	0x0	Disable clock gating for the Render Output Unit of Core 0.
2	RSVD	R		Reserved bit
1		RW	0x0	Disable clock gating for the NemaP Configuration Register File.
0		RW	0x0	Disable clock gating for the Command List Processor.

• Name: Dirty Region Min Register
• Description: This register reads the Dirty_Min value and resets dirty region to resolution size on write function.
• Base Address: 0x40028000
• Offset: 0x98
• Reset Value: 0xFFFFFFFF

表 510 Dirty Region Min Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0xFFFFFFFF	Write any value to reset dirty region to resolution size. Read the Dirty_Min value.

• Name: Dirty Region Max Register
• Description: This register reads the Dirty_Max value.
• Base Address: 0x40028000
• Offset: 0x9C
• Reset Value: 0x00000000

表 511 Dirty Region Max Register

Bits	Field Name	RW	Reset	Description
31:0		R	0x0	Read the Dirty_Max value.

• Name: Load Shader Instruction Memory Address Register
• Description: This register specifies the load shader instruction memory address.
• Base Address: 0x40028000
• Offset: 0xC4
• Reset Value: 0x00000000

表 512 Load Shader Instruction Memory Address Register

Bits	Field Name	RW	Reset	Description
31:4	RSVD	R		Reserved bits
3:0		RW	0x0	Specifies the load shader instruction memory address.

• Name: Lower Bit Data Register
• Description: This register specifies the lower bits (31: 0) of the 64-bit load shader instruction memory data.
• Base Address: 0x40028000
• Offset: 0xC8
• Reset Value: 0x00000000

表 513 Lower Bit Data Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the lower bits (31:0) of the load shader instruction memory data.

• Name: Higher Bit Data Register
• Description: This register specifies the higher bits (63-32) of the 64-bit load shader instruction memory data.
• Base Address: 0x40028000
• Offset: 0xCC
• Reset Value: 0x00000000

表 514 Higher Bit Data Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the higher bits (63-32) of the load shader instruction memory data.

• Name: System Flush Register
• Description: This register controls the system flush.
• Base Address: 0x40028000
• Offset: 0xE4
• Reset Value: 0x00000007

表 515 System Flush Register

Bits	Field Name	RW	Reset	Description
31:14	RSVD	R		Reserved bits
13		RW	0x0	When set to 1, the write caches are flushed.
12	RSVD	R		Reserved bit
11		RW	0x0	If set to 1, the write caches are flushed when the host triggers the rasterizer register (NEMA_DRAW_CMD_NOHOLD).
10:8	RSVD	R		Reserved bits
7		RW	0x0	If set to 1, the write caches are flushed when the Command List Processor triggers the rasterizer register (NEMA_DRAW_CMD_NOHOLD).
6		RW	0x0	When set to 1, the read caches are flushed.
5	RSVD	R		Reserved bit
4		RW	0x0	If set to 1, the read caches are flushed when the host triggers the rasterizer register (NEMA_DRAW_CMD_NOHOLD)
3:1	RSVD	R		Reserved bits
0		RW	0x1	If set to 1, the read caches are flushed when the Command List Processor triggers the rasterizer register (NEMA_DRAW_CMD_NOHOLD).

• Name: Command Status Register
• Description: This register shows the command status.
• Base Address: 0x40028000
• Offset: 0xE8
• Reset Value: 0x00000000

表 516 Command Status Register

Bits	Field Name	RW	Reset	Description
31		RW	0x0	Indicates if the Command List Processor is busy.
30		RW	0x0	Indicates if there are data available in System Memory.
29		RW	0x0	Indicates if there are available data to read from FIFO.
28		RW	0x0	Shows many cells are still available in FIFO.
27:18	RSVD	R		Reserved bits
17:13		RW	0x0	Shows many cells are still available in FIFO.
12	RSVD	R		Reserved bit
11:9		RW	0x0	Shows the address of the stack pointer.
8:7	RSVD	R		Reserved bits
6:4		RW	0x0	Indicates the state of CMDList internal FSM.
3:1	RSVD	R		Reserved bits
0		RW	0x0	Indicates the state of the FSM responsible for fetching.

• Name: Ring Buffer Register
• Description: This register stores the Ring Buffer’s last written address.
• Base Address: 0x40028000
• Offset: 0xEC
• Reset Value: 0x00000000

表 517 Ring Buffer Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Stores the last written address of the ring buffer.

• Name: Command List Base Address Register
• Description: This register specifies the command list base address.
• Base Address: 0x40028000
• Offset: 0xF0
• Reset Value: 0x00000000

表 518 Command List Base Address Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the base address of every new command list ready to be executed.

• Name: Command List Size Register
• Description: This register specifies the command list size.
• Base Address: 0x40028000
• Offset: 0xF4
• Reset Value: 0x00000000

表 519 Command List Size Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the length of the command list ready to be executed.

• Name: Interrupt Control Register
• Description: This register controls the interrupt.
• Base Address: 0x40028000
• Offset: 0xF8
• Reset Value: 0x00000000

表 520 Interrupt Control Register

Bits	Field Name	RW	Reset	Description
31:30		RW	0x0	Specifies the core_clk_dvfs output.
29:28	RSVD	R		Reserved bits
27		RW	0x0	When set to 1, the throttle signal will be ignored.
26:4	RSVD	R		Reserved bits
3		RW	0x0	When set to 1, the interrupt in the NEMA_IRQ_ID register is cleared.
2		RW	0x0	When set to 1, an interrupt is signaled at the end of a drawing command.
1		RW	0x0	When set to 1, an interrupt is signaled at the end of a command list.
0		RW	0x0	1: IRQ signal is active low. 0: IRQ signal is active high.

• Name: GPU Status Register
• Description: This register shows the GPU status.
• Base Address: 0x40028000
• Offset: 0xFC
• Reset Value: 0x00000000

表 521 GPU Status Register

Bits	Field Name	RW	Reset	Description
31		RW	0x0	Indicates if the system is busy.
30		RW	0x0	Indicates if the bus interface unit is busy.
29		RW	0x0	Indicates if the command list bus is busy.
28		RW	0x0	Indicates if the Command List Processor is busy.
27:24		RW	0x0	Indicate if the rasterizer unit is busy.
23:13	RSVD	R		Reserved bits
12		RW	0x0	Indicates if the Core 0 render output unit is busy.
11:9	RSVD	R		Reserved bits
8		RW	0x0	Indicates if the Core 0 texture map unit is busy.
7:5	RSVD	R		Reserved bits
4		RW	0x0	Indicates if the Core 0 graphics pipeline is busy.
3:1	RSVD	R		Reserved bits
0		RW	0x0	Indicates if the Core 0 is busy.

• Name: Rasterizer Command Register
• Description: This register controls the rasterizer.
• Base Address: 0x40028000
• Offset: 0x100
• Reset Value: 0x00000000

表 522 Rasterizer Command Register

Bits	Field Name	RW	Reset	Description
31	RSVD	R		Reserved bit
30		RW	0x0	When set to 1, tile mode is enabled.
29		RW	0x0	When set to 1, positive culling (counter-clockwise) is enabled.
28		RW	0x0	When set to 1, negative culling (clockwise) is enabled.
27		RW	0x0	When set to 1, color gradient is enabled.
26		RW	0x0	When set to 1, antialiasing feature is enabled for edge 0.
25		RW	0x0	When set to 1, antialiasing feature is enabled for edge 1.
24		RW	0x0	When set to 1, antialiasing feature is enabled for edge 2.
23		RW	0x0	When set to 1, antialiasing feature is enabled for edge 3.
22:3	RSVD	R		Reserved bits
2:0		RW	0x0	Draw commands: 0x00: Draw pixels. 0x01: Draw lines. 0x02: Draw rectangles. 0x03: Draw triangles. 0x04: Draw quadrilaterals.

• Name: Draw Start XY Register
• Description: This register specifies the start XY of drawing.
• Base Address: 0x40028000
• Offset: 0x104
• Reset Value: 0x00000000

表 523 Draw Start XY Register

Bits	Field Name	RW	Reset	Description
31:16		RW	0x0	Specifies the Y coordinate (integer value) of vertex 0.
15:0		RW	0x0	Specifies the X coordinate (integer value) of vertex 0.

• Name: Draw End XY Register
• Description: This register specifies the end XY of drawing.
• Base Address: 0x40028000
• Offset: 0x108
• Reset Value: 0x00000000

表 524 Draw End XY Register

Bits	Field Name	RW	Reset	Description
31:16		RW	0x0	Specifies the Y coordinate (integer value) of vertex 1.
15:0		RW	0x0	Specifies the X coordinate (integer value) of vertex 1.

• Name: Clip Min Register
• Description: This register specifies clipping rectangle upper left vertex.
• Base Address: 0x40028000
• Offset: 0x110
• Reset Value: 0x00000000

表 525 Clip Min Register

Bits	Field Name	RW	Reset	Description
31:16		RW	0x0	Defines the upper left Y coordinate.
15:0		RW	0x0	Defines the upper left X coordinate.

• Name: Clip Max Register
• Description: This register specifies clipping rectangle bottom right vertex.
• Base Address: 0x40028000
• Offset: 0x114
• Reset Value: 0x00000000

表 526 Clip Max Register

Bits	Field Name	RW	Reset	Description
31:16		RW	0x0	Defines the bottom right Y coordinate.
15:0		RW	0x0	Defines the bottom right X coordinate.

• Name: Matrix Multiplication Control Register
• Description: This register controls the rasterizer matrix multiplication.
• Base Address: 0x40028000
• Offset: 0x118
• Reset Value: 0x00000000

表 527 Matrix Multiplication Control Register

Bits	Field Name	RW	Reset	Description
31:30	RSVD	R		Reserved bits
29		RW	0x0	When set to 1, the 0.5 value is added to the X and Y coordinates.
28		RW	0x0	When set to 1, the matrix multiplications are bypassed.
27		RW	0x0	When set to 0, the result is in fixed point value (default).
26		RW	0x0	When set to 1, the result is in floating point value.
25:0	RSVD	R		Reserved bits

• Name: Shader Code Register
• Description: This register specifies the pointer of the shader code.
• Base Address: 0x40028000
• Offset: 0x11C
• Reset Value: 0x00000000

表 528 Shader Code Register

Bits	Field Name	RW	Reset	Description
31:16		RW	0x0	Specifies the pointer for the instruction that will be executed for the background pixels.
15:0		RW	0x0	Specifies the pointer for the instruction that will be executed for the foreground pixels.

• Name: Vertex 0 Draw X Register
• Description: This register specifies the X coordinate of vertex 0 drawing primitive.
• Base Address: 0x40028000
• Offset: 0x120
• Reset Value: 0x00000000

表 529 Vertex 0 Draw X Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the X coordinate of vertex 0 drawing primitive (16.16 fixed point).

• Name: Vertex 0 Draw Y Register
• Description: This register specifies the Y coordinate of vertex 0 drawing primitive.
• Base Address: 0x40028000
• Offset: 0x124
• Reset Value: 0x00000000

表 530 Vertex 0 Draw Y Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the Y coordinate of vertex 0 drawing primitive (16.16 fixed point).

• Name: Drawing Color Register
• Description: This register specifies the drawing color for filling primitives.
• Base Address: 0x40028000
• Offset: 0x12C
• Reset Value: 0x00000000

表 531 Drawing Color Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the drawing color for filling primitives.

• Name: Vertex 1 Draw X Register
• Description: This register specifies the X coordinate of vertex 1 drawing primitive.
• Base Address: 0x40028000
• Offset: 0x130
• Reset Value: 0x00000000

表 532 Vertex 1 Draw X Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the X coordinate of vertex 1 drawing primitive (16.16 fixed point).

• Name: Vertex 1 Draw Y Register
• Description: This register specifies the Y coordinate of vertex 1 drawing primitive.
• Base Address: 0x40028000
• Offset: 0x134
• Reset Value: 0x00000000

表 533 Vertex 1 Draw Y Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the Y coordinate of vertex 1 drawing primitive (16.16 fixed point).

• Name: Bypass Address Register
• Description: This register shows the address of bypass mode of rasterizer setup access.
• Base Address: 0x40028000
• Offset: 0x138
• Reset Value: 0x00000000

表 534 Bypass Address Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Sets the address of bypass mode of rasterizer setup access.

• Name: Bypass Data Register
• Description: This register shows the data and enablement of bypass mode of rasterizer.
• Base Address: 0x40028000
• Offset: 0x13C
• Reset Value: 0x00000000

表 535 Bypass Data Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Shows data and enablement of bypass mode of rasterizer.

• Name: Vertex 2 Draw X Register
• Description: This register specifies the X coordinate of vertex 2 drawing primitive.
• Base Address: 0x40028000
• Offset: 0x140
• Reset Value: 0x00000000

表 536 Vertex 2 Draw X Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the X coordinate of vertex 2 drawing primitive (16.16 fixed point).

• Name: Vertex 2 Draw Y Register
• Description: This register specifies the Y coordinate of vertex 2 drawing primitive.
• Base Address: 0x40028000
• Offset: 0x144
• Reset Value: 0x00000000

表 537 Vertex 2 Draw Y Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the Y coordinate of vertex 2 drawing primitive (16.16 fixed point).

• Name: Command List ID Register
• Description: This register specifies the last executed command list.
• Base Address: 0x40028000
• Offset: 0x148
• Reset Value: 0x00000000

表 538 Command List ID Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the last executed command list.

• Name: Vertex 3 Draw X Register
• Description: This register specifies the X coordinate of vertex 3 drawing primitive.
• Base Address: 0x40028000
• Offset: 0x150
• Reset Value: 0x00000000

表 539 Vertex 3 Draw X Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the X coordinate of vertex 3 drawing primitive (16.16 fixed point).

• Name: Vertex 3 Draw Y Register
• Description: This register specifies the Y coordinate of vertex 3 drawing primitive.
• Base Address: 0x40028000
• Offset: 0x154
• Reset Value: 0x00000000

表 540 Vertex 3 Draw Y Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the Y coordinate of vertex 3 drawing primitive (16.16 fixed point).

• Name: Clip Min Register 1
• Description: This register specifies the second clipping rectangle upper left vertex.
• Base Address: 0x40028000
• Offset: 0x158
• Reset Value: 0x00000000

表 541 Clip Min Register 1

Bits	Field Name	RW	Reset	Description
31:16		RW	0x0	Defines the upper left Y coordinate.
15:0		RW	0x0	Defines the upper left X coordinate.

• Name: Clip Max Register 1
• Description: This register specifies the second clipping rectangle bottom right vertex.
• Base Address: 0x40028000
• Offset: 0x15C
• Reset Value: 0x7FFF7FFF

表 542 Clip Max Register 1

Bits	Field Name	RW	Reset	Description
31:16		RW	0x7FFF	Defines the bottom right Y coordinate.
15:0		RW	0x7FFF	Defines the bottom right X coordinate.

• Name: (0,0) Matrix Register
• Description: This register specifies the (0,0) matrix floating point element.
• Base Address: 0x40028000
• Offset: 0x160
• Reset Value: 0x00000000

表 543 (0,0) Matrix Register

Bits	Field Name	RW	Reset	Description
31:21	RSVD	R		Reserved bits
20:0		RW	0x0	Specifies the (0,0) element.

• Name: (0,1) Matrix Register
• Description: This register specifies the (0,1) matrix floating point element.
• Base Address: 0x40028000
• Offset: 0x164
• Reset Value: 0x00000000

表 544 (0,1) Matrix Register

Bits	Field Name	RW	Reset	Description
31:21	RSVD	R		Reserved bits
20:0		RW	0x0	Specifies the (0,1) element.

• Name: (0,2) Matrix Register
• Description: This register specifies the (0,2) matrix floating point element.
• Base Address: 0x40028000
• Offset: 0x168
• Reset Value: 0x00000000

表 545 (0,2) Matrix Register

Bits	Field Name	RW	Reset	Description
31:21	RSVD	R		Reserved bits
20:0		RW	0x0	Specifies the (0,2) element.

• Name: (1,0) Matrix Register
• Description: This register specifies the (1,0) matrix floating point element.
• Base Address: 0x40028000
• Offset: 0x16C
• Reset Value: 0x00000000

表 546 (1,0) Matrix Register

Bits	Field Name	RW	Reset	Description
31:21	RSVD	R		Reserved bits
20:0		RW	0x0	Specifies the (1,0) element.

• Name: (1,1) Matrix Register
• Description: This register specifies the (1,1) matrix floating point element.
• Base Address: 0x40028000
• Offset: 0x170
• Reset Value: 0x00000000

表 547 (1,1) Matrix Register

Bits	Field Name	RW	Reset	Description
31:21	RSVD	R		Reserved bits
20:0		RW	0x0	Specifies the (1,1) element.

• Name: (1,2) Matrix Register
• Description: This register specifies the (1,2) matrix floating point element.
• Base Address: 0x40028000
• Offset: 0x174
• Reset Value: 0x00000000

表 548 (1,2) Matrix Register

Bits	Field Name	RW	Reset	Description
31:21	RSVD	R		Reserved bits
20:0		RW	0x0	Specifies the (1,2) element.

• Name: (2,0) Matrix Register
• Description: This register specifies the (2,0) matrix floating point element.
• Base Address: 0x40028000
• Offset: 0x178
• Reset Value: 0x00000000

表 549 (2,0) Matrix Register

Bits	Field Name	RW	Reset	Description
31:21	RSVD	R		Reserved bits
20:0		RW	0x0	Specifies the (2,0) element.

• Name: (2,1) Matrix Register
• Description: This register specifies the (2,1) matrix floating point element.
• Base Address: 0x40028000
• Offset: 0x17C
• Reset Value: 0x00000000

表 550 (2,1) Matrix Register

Bits	Field Name	RW	Reset	Description
31:21	RSVD	R		Reserved bits
20:0		RW	0x0	Specifies the (2,1) element.

• Name: (2,2) Matrix Register
• Description: This register specifies the (2,2) matrix floating point element.
• Base Address: 0x40028000
• Offset: 0x180
• Reset Value: 0x00000000

表 551 (2,2) Matrix Register

Bits	Field Name	RW	Reset	Description
31:21	RSVD	R		Reserved bits
20:0		RW	0x0	Specifies the (2,2) element.

• Name: Integral Depth Value Low Register
• Description: This register specifies the integral part of lower 32-bit depth value of the STARTXY pixel.
• Base Address: 0x40028000
• Offset: 0x184
• Reset Value: 0x00000000

表 552 Integral Depth Value Low Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the integral part of the depth value of the STARTXY pixel.

• Name: Integral Depth Value High Register
• Description: This register specifies the integral part of higher 32-bit depth value of the STARTXY pixel.
• Base Address: 0x40028000
• Offset: 0x188
• Reset Value: 0x00000000

表 553 Integral Depth Value High Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the integral value of the depth value of the STARTXY pixel.

• Name: Fractional X Depth Value Low Register
• Description: This register specifies the fractional part of lower 32-bit depth value for each step at X axis.
• Base Address: 0x40028000
• Offset: 0x18C
• Reset Value: 0x00000000

表 554 Fractional X Depth Value Low Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the fractional part of the added depth value for each step at X axis.

• Name: Integral X Depth Value High Register
• Description: This register specifies the integral part of higher 32-bit depth value for each step at X axis.
• Base Address: 0x40028000
• Offset: 0x190
• Reset Value: 0x00000000

表 555 Integral X Depth Value High Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the integral part of the added depth value for each step at X axis.

• Name: Fractional Y Depth Value Low Register
• Description: This register specifies the fractional part of lower 32-bit depth value for each step at Y axis.
• Base Address: 0x40028000
• Offset: 0x194
• Reset Value: 0x00000000

表 556 Fractional Y Depth Value Low Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the fractional part of the added depth value for each step at Y axis.

• Name: Integral Y Depth Value High Register
• Description: This register specifies the integral part of higher 32-bit depth value for each step at Y axis.
• Base Address: 0x40028000
• Offset: 0x198
• Reset Value: 0x00000000

表 557 Integral Y Depth Value High Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the integral part of the added depth value for each step at Y axis.

• Name: Red (R) Value X Register
• Description: This register specifies the added Red (R) value for each step at X axis.
• Base Address: 0x40028000
• Offset: 0x1A0
• Reset Value: 0x00000000

表 558 Red (R) Value X Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the added Red (R) value for each step at X axis.

• Name: Red (R) Value Y Register
• Description: This register specifies the added Red (R) value for each step at Y axis.
• Base Address: 0x40028000
• Offset: 0x1A4
• Reset Value: 0x00000000

表 559 Red (R) Value Y Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the added Red (R) value for each step at Y axis.

• Name: Green (G) Value X Register
• Description: This register specifies the added Green (G) value for each step at X axis.
• Base Address: 0x40028000
• Offset: 0x1A8
• Reset Value: 0x00000000

表 560 Green (G) Value X Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the added Green (G) value for each step at X axis.

• Name: Green (G) Value Y Register
• Description: This register specifies the added Green (G) value for each step at Y axis.
• Base Address: 0x40028000
• Offset: 0x1AC
• Reset Value: 0x00000000

表 561 Green (G) Value Y Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the added Green (G) value for each step at Y axis.

• Name: Blue (B) Value X Register
• Description: This register specifies the added Blue (B) value for each step at X axis.
• Base Address: 0x40028000
• Offset: 0x1B0
• Reset Value: 0x00000000

表 562 Blue (B) Value X Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the added Blue (B) value for each step at X axis.

• Name: Blue (B) Value Y Register
• Description: This register specifies the added Blue (B) value for each step at Y axis.
• Base Address: 0x40028000
• Offset: 0x1B4
• Reset Value: 0x00000000

表 563 Blue (B) Value Y Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the added Blue (B) value for each step at Y axis.

• Name: Alpha (A) Value X Register
• Description: This register specifies the added Alpha (A) value for each step at X axis.
• Base Address: 0x40028000
• Offset: 0x1B8
• Reset Value: 0x00000000

表 564 Alpha (A) Value X Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the added Alpha (A) value for each step at X axis.

• Name: Alpha (A) Value Y Register
• Description: This register specifies the added Alpha (A) value for each step at Y axis.
• Base Address: 0x40028000
• Offset: 0x1BC
• Reset Value: 0x00000000

表 565 Alpha (A) Value Y Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the added Alpha (A) value for each step at Y axis.

• Name: Red (R) Value Init Register
• Description: This register specifies the Red (R) value of the STARTXY pixel.
• Base Address: 0x40028000
• Offset: 0x1C0
• Reset Value: 0x00000000

表 566 Red (R) Value Init Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the Red (R) value of the STARTXY pixel.

• Name: Green (G) Value Init Register
• Description: This register specifies the Green (G) value of the STARTXY pixel.
• Base Address: 0x40028000
• Offset: 0x1C4
• Reset Value: 0x00000000

表 567 Green (G) Value Init Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the Green (G) value of the STARTXY pixel.

• Name: Blue (B) Value Init Register
• Description: This register specifies the Blue (B) value of the STARTXY pixel.
• Base Address: 0x40028000
• Offset: 0x1C8
• Reset Value: 0x00000000

表 568 Blue (B) Value Init Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the Blue (B) value of the STARTXY pixel.

• Name: Alpha (A) Value Init Register
• Description: This register specifies the Alpha (A) value of the STARTXY pixel.
• Base Address: 0x40028000
• Offset: 0x1CC
• Reset Value: 0x00000000

表 569 Alpha (A) Value Init Register

Bits	Field Name	RW	Reset	Description
31:0		RW	0x0	Specifies the Alpha (A) value of the STARTXY pixel.

• Name: Blending Mode Register
• Description: This register specifies the blending modes for different calculations between the source (Fragment Processing Core) and destination (Framebuffer) colors.
• Base Address: 0x40028000
• Offset: 0x1D0
• Reset Value: 0x00000000

表 570 Blending Mode Register

Bits	Field Name	RW	Reset	Description
31		RW	0x0	If set, destination color keying is enabled.
30		RW	0x0	If set, source color keying is enabled.
29:26	RSVD	R		Reserved bits
25		RW	0x0	If set, negative destination color keying is enabled.
24:12	RSVD	R		Reserved bits
11:8		RW	0x0	Indicates the blending mode of the stored pixel in the Framebuffer (destination pixel).
7:4	RSVD	R		Reserved bits
3:0		RW	0x0	Indicates the blending mode of the current pixel (source pixel).