Block Diagram
图 152 shows the following functional groupings of the main interfaces to the DMA controller block:
- DMA hardware request interface
- 6 channels
- 128 bytes FIFO for Channel 0 and 32 bytes FIFO per other channel for source and destination
- Arbiter
- AHB master interface
- AHB slave interface
图 153 illustrates a peripheral-to-peripheral DMA transfer, where Peripheral A (source) uses a hardware handshaking interface, and Peripheral B (destination) uses a software handshaking interface. For example, the request to send data to Peripheral B is originated by the CPU, while writing to Peripheral B is handled by the DMA controller. The channel source and destination arbitrate independently for the AHB master interface, along with other channels.
