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GR5525 Datasheet

版本：

V1.2

V1.4 V1.2 Rev.1.1 V1.0

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文档中心 > GR5525 Datasheet/ Peripherals/ Pin Mux/ Functional Description Copy URL

Functional Description

The pin multiplexing choices for all pads are shown in:

Table 260 and Table 261 (GPIO_0–GPIO_15)
Table 262 and Table 263 (GPIO_16–GPIO_33)
Table 264 (MSIO_0–MSIO_7)
Table 265 (AON_GPIO_0–AON_GPIO_7)

There are eight mux choices (from MUX_0 to MUX_7) in the pin mux tables as follows.

Table 260 Pin multiplexing for GPIO_0–GPIO_7
IO Name	MUX_0	MUX_1	MUX_2	MUX_3	MUX_4	MUX_5	MUX_6	MUX_7	MUX_8
GPIO_0	SWD_CLK	I2C0_SCL	I2C1_SCL	UART1_RTS	UART0_TX	UART1_TX	UART0_RTS	PDM_CLKO	GPIO_A0
GPIO_1	SWD_IO	I2C0_SDA	I2C1_SDA	UART1_CTS	UART0_RX	UART1_RX	UART0_CTS	PDM_DI	GPIO_A1
GPIO_2	UART0_CTS	PDM_CLKO	SWO	SPI_S_CS_N	I2C0_SDA	PWM0_A	FERP_GPIO_Trig	QSPI_M2_IO_2	GPIO_A2
GPIO_3	UART0_TX	PDM_DI	SPI_M_CLK	SPI_S_CLK	SPI_M_CS1_N	PWM0_B	DSPI_SCK	QSPI_M2_CLK	GPIO_A3
GPIO_4	UART0_RX	I2C2_SDA	SPI_M_MOSI	SPI_S_MISO	SPI_M_CS0_N	PWM0_C	DSPI_MOSI	QSPI_M2_IO_0	GPIO_A4
GPIO_5	UART0_RTS	I2C2_SCL	SPI_M_MISO	SPI_S_MOSI	SPI_M_MISO	I2C0_SCL	DSPI_MISO	QSPI_M2_IO_1	GPIO_A5
GPIO_6	I2S_WS	I2S_S_WS	SPI_M_CS0_N	UART1_RX	SPI_M_MOSI	I2C0_SDA	DSPI_NSS	QSPI_M2_CS_N	GPIO_A6
GPIO_7	I2S_TX_SDO	I2S_S_TX_SDO	SPI_M_CS1_N	UART1_TX	SPI_M_CLK	PWM1_A	DSPI_DCX	QSPI_M2_IO_3	GPIO_A7

Table 261 Pin multiplexing for GPIO_8–GPIO_15
IO Name	MUX_0	MUX_1	MUX_2	MUX_3	MUX_4	MUX_5	MUX_6	MUX_7	MUX_8
GPIO_8	QSPI_M0_IO_0	I2C1_SDA	QSPI_M1_IO_0	UART1_RX	PWM0_A	PWM1_B	PWM0_C		GPIO_A8
GPIO_9	QSPI_M0_CLK	I2C1_SCL	QSPI_M1_CLK	UART1_TX	PWM0_B	PWM1_C	PWM1_A		GPIO_A9
GPIO_10	I2S_RX_SDI	I2S_S_RX_SDI	UART0_TX	I2C3_SCL	I2C0_SCL	PWM1_B		QSPI_M1_IO_2	GPIO_A10
GPIO_11	I2S_SCLK	I2S_S_SCLK	UART0_RX	I2C3_SDA	I2C0_SDA	PWM1_C	SWO	QSPI_M1_IO_3	GPIO_A11
GPIO_12	QSPI_M0_IO_3	SPI_M_CLK	QSPI_M1_IO_3	UART2_TX	I2S_WS	I2S_S_WS	SPI_S_CS_N		GPIO_A12
GPIO_13	QSPI_M0_IO_2	SPI_M_MOSI	QSPI_M1_IO_2	UART2_RX	I2S_TX_SDO	I2S_S_TX_SDO	SPI_S_CLK		GPIO_A13
GPIO_14	QSPI_M0_IO_1	SPI_M_MISO	QSPI_M1_IO_1	UART2_RTS	I2S_RX_SDI	I2S_S_RX_SDI	SPI_S_MISO		GPIO_A14
GPIO_15	QSPI_M0_CS_N	SPI_M_CS0_N	QSPI_M1_CS_N	UART2_CTS	I2S_SCLK	I2S_S_SCLK	SPI_S_MOSI	FERP_GPIO_Trig	GPIO_A15

Table 262 Pin multiplexing for GPIO_16–GPIO_23
IO Name	MUX_0	MUX_1	MUX_2	MUX_3	MUX_4	MUX_5	MUX_6	MUX_7	MUX_8
GPIO_16	SPI_M_MISO	SPI_S_MOSI	DSPI_MISO	I2S_RX_SDI	I2S_S_RX_SDI	QSPI_M1_IO_1	FERP_GPIO_Trig	UART3_RTS	GPIO_B0
GPIO_17	SPI_M_CS0_N	SPI_S_CS_N	DSPI_NSS	I2S_SCLK	I2S_S_SCLK	QSPI_M1_IO_2		UART3_CTS	GPIO_B1
GPIO_18	QSPI_M0_CLK	SPI_M_CS1_N		I2C3_SCL	UART3_TX		I2C1_SCL	QSPI_M1_CLK	GPIO_B2
GPIO_19	QSPI_M0_IO_0			I2C3_SDA	UART3_RX		I2C1_SDA	QSPI_M1_IO_1	GPIO_B3
GPIO_20	I2C2_SCL			QSPI_M2_IO_0	UART3_RTS	PDM_CLKO	df_ant_switch_sel_5	QSPI_M1_IO_0	GPIO_B4
GPIO_21	I2C2_SDA		DSPI_DCX	QSPI_M2_CS_N	UART3_CTS	PDM_DI	df_ant_switch_sel_6	QSPI_M1_CS_N	GPIO_B5
GPIO_22	SPI_S_CLK	I2S_WS	DSPI_SCK	QSPI_M2_CLK	I2S_S_WS	SPI_M_CLK	df_ant_switch_sel_0	QSPI_M1_CLK	GPIO_B6
GPIO_23	SPI_S_MISO	I2S_TX_SDO	DSPI_MOSI	QSPI_M2_IO_1	I2S_S_TX_SDO	SPI_M_MOSI	df_ant_switch_sel_1	QSPI_M1_IO_1	GPIO_B7

Table 263 Pin multiplexing for GPIO_24–GPIO_33
IO Name	MUX_0	MUX_1	MUX_2	MUX_3	MUX_4	MUX_5	MUX_6	MUX_7	MUX_8
GPIO_24	SPI_M_CLK	SPI_S_CLK	DSPI_SCK	I2S_WS	I2S_S_WS	QSPI_M1_CLK		UART3_TX	GPIO_B8
GPIO_25	SPI_M_MOSI	SPI_S_MISO	DSPI_MOSI	I2S_TX_SDO	I2S_S_TX_SDO	QSPI_M1_IO_0		UART3_RX	GPIO_B9
GPIO_26	I2C1_SDA	UART1_RX	I2C0_SDA	PWM0_C	PWM1_C	UART0_RX	df_ant_switch_sel_1	QSPI_M2_IO_0	GPIO_B10
GPIO_27	PDM_CLKO	UART1_RTS			I2C2_SCL	UART0_RTS	df_ant_switch_sel_2	QSPI_M2_IO_1	GPIO_B11
GPIO_28	PDM_DI	UART1_CTS			I2C2_SDA	UART0_CTS	df_ant_switch_sel_3	QSPI_M2_IO_2	GPIO_B12
GPIO_29	FERP_GPIO_Trig			PWM1_A	PWM0_C		df_ant_switch_sel_4	QSPI_M2_IO_3	GPIO_B13
GPIO_30	I2C1_SCL	UART1_TX	I2C0_SCL	PWM0_B	PWM1_B	UART0_TX		QSPI_M2_CLK	GPIO_B14
GPIO_31	SPI_M_CS1_N	FERP_GPIO_Trig	DSPI_DCX	PWM0_A	PWM1_A	QSPI_M1_IO_3		df_ant_switch_sel_0	GPIO_B15
GPIO_32	SPI_S_MOSI	I2S_RX_SDI	DSPI_MISO	QSPI_M2_IO_2	I2S_S_RX_SDI	SPI_M_MISO	df_ant_switch_sel_2	QSPI_M1_IO_2	GPIO_C0
GPIO_33	SPI_S_CS_N	I2S_SCLK	DSPI_NSS	QSPI_M2_IO_3	I2S_S_SCLK	SPI_M_CS0_N	df_ant_switch_sel_3	QSPI_M1_IO_3	GPIO_C1

Table 264 Pin multiplexing for MSIO_0–MSIO_7
IO Name	MUX_0	MUX_1	MUX_2	MUX_3	MUX_4	MUX_5	MUX_6	MUX_7	MUX_8
MSIO_0	PWM0_A	UART0_TX	UART1_TX	I2C0_SCL	I2C2_SCL	I2C1_SCL	I2C3_SCL	df_ant_switch_sel_0	MSIO_0
MSIO_1	PWM0_B	UART0_RX	UART1_RX	I2C0_SDA	I2C2_SDA	I2C1_SDA	I2C3_SDA	df_ant_switch_sel_1	MSIO_1
MSIO_2	PWM0_C							df_ant_switch_sel_2	MSIO_2
MSIO_3	PWM1_A	UART0_RTS	UART1_RTS	I2C1_SCL	I2C3_SCL	I2C0_SCL	I2C2_SCL	df_ant_switch_sel_3	MSIO_3
MSIO_4	PWM1_B	UART0_CTS	UART1_CTS	I2C1_SDA	I2C3_SDA	I2C0_SDA	I2C2_SDA	df_ant_switch_sel_4	MSIO_4
MSIO_5	PWM1_C			UART2_RTS	UART3_TX	UART2_TX	UART3_RTS	df_ant_switch_sel_5	MSIO_5
MSIO_6				UART2_CTS	UART3_RX	UART2_RX	UART3_CTS	df_ant_switch_sel_6	MSIO_6
MSIO_7									MSIO_7

Table 265 Pin multiplexing for AON_GPIO_0–AON_GPIO_7
IO Name	MUX_0	MUX_1	MUX_2	MUX_3	MUX_4	MUX_5	MUX_6	MUX_7	MUX_8
AON_GPIO_0		QSPI_M0_IO_2		I2C2_SCL	I2C1_SCL			df_ant_switch_sel_5	AON_GPIO_0
AON_GPIO_1		QSPI_M0_IO_3	DSPI_NSS	I2C2_SDA	I2C1_SDA	QSPI_M1_CS_N		DSPI_DCX	AON_GPIO_1
AON_GPIO_2	UART2_CTS	QSPI_M0_CS_N	I2S_WS	I2S_S_WS	UART3_CTS	PWM0_C		DSPI_NSS	AON_GPIO_2
AON_GPIO_3	UART2_TX	QSPI_M0_IO_0	I2S_TX_SDO	I2S_S_TX_SDO	UART3_TX	PWM1_A		DSPI_MOSI	AON_GPIO_3
AON_GPIO_4	UART2_RX	QSPI_M0_IO_1	I2S_RX_SDI	I2S_S_RX_SDI	UART3_RX	PWM1_B		DSPI_MISO	AON_GPIO_4
AON_GPIO_5	UART2_RTS	QSPI_M0_CLK	I2S_SCLK	I2S_S_SCLK	UART3_RTS	PWM1_C		DSPI_SCK	AON_GPIO_5
AON_GPIO_6							df_ant_switch_sel_5	df_ant_switch_sel_6	AON_GPIO_6
AON_GPIO_7							df_ant_switch_sel_6	QSPI_M2_CS_N	AON_GPIO_7

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