Sleep Timer (SLP TIMER)

Introduction

The Sleep Timer is a 32-bit hardware timer that can wake the SoC up from the Deep Sleep state. It can also be used while the SoC is awake.

32-bit down counter running with two different clock sources: LFXO_32K clock (32.768 kHz), and LFRC_32K clock (about 32 kHz).
Three operation modes: Basic Sleep Timer, Single-load Sleep Timer, Auto-reload Sleep Timer.

The Sleep Timer supports three operation modes.

Mode 0 – Basic Sleep Timer: This is the original mode of the Sleep Timer. It only counts down when the SoC is in Deep Sleep state and is not activated when the SoC is awake.
Mode 1 – Single-load Sleep Timer: In this mode, the timer starts counting as soon as it is put in this mode and it continues to count down even when the SoC is awake. The timer stops when the counter hits zero. The time-out signal is saved as a timeout event.
Mode 2 – Auto-reload Sleep Timer: Similar to Single-load Sleep Timer mode, the timer does not stop counting down even when the SoC is awake. However, the timer can automatically reload to a value that is the same as that before automatic reload until it is disabled by the MCU.

Table 346 CFG_0 Register
Bits	Field Name	RW	Reset	Description
24	SLP_TIME_CFG	W	N/A	Write: Writing 1 to this register triggers the Sleep Timer configuration. Writing to this bit during sleep timer configuration will generate a configuration failure interrupt. Read: The read value is always 0.
3	SLP_TIMER_CNT_SLP_ONLY	RW	0x0	Value: 0x1: Count during sleep only. 0x0: Count in any condition.
2	SLP_TIMER_SINGLE_EN	RW	0x0	Value: 0x1: Single-load mode 0x0: Auto reload mode
1	SLP_TIMER_SET	RW	0x0	Sets the timer value; write 1 to make timer value effective.
0	SLP_TIMER_EN	RW	0x0	Enables Sleep Timer. Value: 0x1: Enable Sleep Timer. 0x0: Disable Sleep Timer.

Table 347 STS Register
Bits	Field Name	RW	Reset	Description
1	SLP_TIMER_BUSY	R	N/A	Sleep Timer is running.
0	SLP_TIMER_STATUS	R	N/A	Sleep Timer is busy. Do not configure this bit if the signal is 1.

Table 348 CLK Register
Bits	Field Name	RW	Reset	Description
1:0	SLP_TIMER_CLK_SEL	RW	0x0	Selects Sleep Timer clock. Value: 0x02: LFRC_32K (LFRC 32 kHz Clock) 0x03: LFXO_32K (LF_XO 32 kHz Clock)

Table 349 VAL_W Register
Bits	Field Name	RW	Reset	Description
31:0	SLP_TIMER_VAL_SET	RW	0x0	Write: Write the Sleep Timer value to the VAL_W register. Read: The value you just set. Read SLP_TIMER_VAL_RD in the VAL_R register for the current interval value.

Table 350 VAL_R
Bits	Field Name	RW	Reset	Description
31:0	SLP_TIMER_VAL_RD	R	N/A	Read internal value of the Sleep Timer.