Always-On I/O

Introduction

The Always-on Watchdog(AON_WDT) is a 32-bit countdown hardware timer. When the AON_WDT counter counts to 0, a system reset signal is sent, and when the counter value decreases to the set warning value, an interrupt signal is generated. Because the AON_WDT timer is in the AON domain, it can keep running when the MCU is off.

Functional Description

The LOCK register enables or disables write accesses to all other registers. This is to prevent malicious software from disabling the watchdog functionality. Writing a value of 0x15CC5A51 (LOCK.LOCK_SET[31:1]) enables write accesses to all other registers. Writing any other value to the LOCK register disables the write accesses.
When the AON_WDT is disabled, all register values must be cleared to restore the default values.
When the CFG0.EN bit is set to 1, the value of the TIMER_W register is automatically loaded into the TIMER_R register, and the value starts to decrease.
The AON_WDT alarm interrupt is triggered when the value of the TIMER_R register decrements to the value of the ALARM_R register.
When the TIMER_R count value decrements to 0, the system restarts.

Registers

AON_PAD_CTRL0

Name: Always-on Pad Control Register
Description: This register contains the AON_GPIO configurations.
Base Address: 0x4000A000
Offset: 0x1E4
Reset Value: 0x00FF0000

Table 294 AON_PAD_CTRL_0 Register
Bits	Field Name	RW	Reset	Description
31:24	AON_INPUT_VAL	R	0x0	Always-on PAD signal from outside to cores
16:23	AON_IN_N	RW	0xFF	Always-on PAD input enable Value: 0x0: Disable AONx input. 0x1: Enable AONx input
15:8	AON_O_N	RW	0x0	Always-on PAD output enable Value: 0x0: Disable AONx output. 0x1: Enable AONx output.
7:0	AON_OUT_VAL	RW	0x0	Always-on PAD signal from core to outside

AON_PAD_CTRL1

Name: Always-on Pad Control Register
Description: This register contains the input and output data.
Base Address: 0x4000A000
Offset: 0x1E8
Reset Value: 0x000000FF

Table 295 AON_PAD_CTRL_1 Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:8	AON_R_TYPE	RW	0x00	Always-on PAD resistor type Value: 0x0: pull-down 0x1: pull-up
7:0	AON_RE_N	RW	0xFF	Always-on PAD resistor enable Value: 0x0: Disable AONx resistor. 0x1: Enable AONx resistor.

AON_PAD_CLK

Name: Always-on PAD output clock controls register
Description: This register controls inner clock output from AON_GPIO_4.
Base Address: 0x4000A000
Offset: 0x1F0
Reset Value: 0x00000000

Table 296 AON_PAD_CLK Register
Bits	Field Name	RW	Reset	Description
31:5	RSVD	R		Reserved bits
4:2	CLK_OUT_SEL	RW	0x0	Clock out selection Value: 0x0: RNG_OSC (RNG Osc 32 kHz Clock) 0x1: HFXO_32K (HFXO 32 kHz derived from HFXO_32 MHz Clock) 0x2: LFRC_32K (LFRC 32 kHz Clock) 0x3: LFXO_32K (LF_XO 32 kHz Clock)
1	RSVD	R		Reserved bits
0	CLK_OUT_EN	RW	0x0	Enable clock out via AON GPIO 4. Value: 0x0: Disable selected clock out via AON GPIO 4. 0x1: Enable selected clock out via AON GPIO 4.

AON_PAD_MCU_OVR

Name: Always-on Pad Control Register
Description: This register controls the MCU domain setting of always-on pads.
Base Address: 0x4000A000
Offset: 0x1F4
Reset Value: 0x00000000

Table 297 AON_PAD_MCU_OVR Register
Bits	Field Name	RW	Reset	Description
31:17	RSVD	R		Reserved bits
23:16	AON_PAD_MCU_OVR	RW	0x0	Use the settings from MCU domain; only valid when MCU domain is ON 0x0: Disable AONx digital setting. 0x1: Enable AONx digital setting.
15:0	RSVD	R		Reserved bits

Electrical Specifications

The electrical parameters for the AON_GPIO_0–AON_GPIO_7 are as follows:

Table 298 GPIO electrical specifications
Parameter	Description	Min.	Typ.	Max.	Unit
V_IH	Input high voltage	VDDIO x 0.7		VDDIO	V
V_IL	Input low voltage	VSSIO		VDDIO x 0.3	V
V_OH,L	Output high voltage, 4 mA, VDD ≥ 1.7 V	VDD – 0.4		VDD	V
V_OH,M	Output high voltage, 4 mA, VDD ≥ 2.5 V	VDD – 0.4		VDD	V
V_OH,H	Output high voltage, 4 mA, VDD ≥ 3 V	VDD – 0.4		VDD	V
V_OL,L	Output low voltage, 4 mA, VDD ≥ 1.7 V	VSS		VSS + 0.4	V
V_OL,M	Output low voltage, 4 mA, VDD ≥ 2.5 V	VSS		VSS + 0.4	V
V_OL,H	Output low voltage, 4 mA, VDD ≥ 3 V	VSS		VSS + 0.4	V
I_OL	Current at VSS+0.4 V, output set low, VDD ≥1.7 V		4		mA
I_OH	Current at VDD-0.4 V, output set high, VDD ≥ 1.7 V		4		mA
R_PU	Pull-up resistance		20		kΩ
R_PD	Pull-down resistance		20		kΩ
C_PAD	Pad capacitance		5		pF