Mixed Signal I/O
Introduction
The device has eight individually configurable MSIOs that can be applied by peripherals, digital input\output or analog input.
Functional Description
- MSIO default state is analog input mode.
- As analog input for sense ADC or Comparator.
- As digital MSIOs for input/output, no interrupt.
- To multiplex some different peripherals.
- For digital modules with high timing requirements, it is recommended to increase the MSIO drive current.
Registers
MSIO_APAD_CFG0
- Name: MSIO Pad Control Register
- Description: This register contains the input and output data.
- Base Address: 0x4000A1D4
- Offset: 0x00
- Reset Value: 0x00FF0000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:24 |
MSIO_VAL |
R |
MSIO read value |
|
23:16 |
MSIO_IE_N |
RW |
0xFF |
MSIO input enable Value:
|
15:8 |
MSIO_OE_N |
RW |
0x0 |
MSIOA output enable (active low) Value:
|
7:0 |
MSIO_OUT |
RW |
0x0 |
MSIO output value (valid in output mode) |
MSIO_APAD_CFG1
- Name: MSIO Pad Control Register
- Description: This register contains the MSIOA configurations.
- Base Address: 4000A1D8
- Offset: 0x00
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:16 |
RSVD |
R |
Reserved bits |
|
15:8 |
MSIO_RTYPE |
RW |
0x0 |
MSIO resistor type Value:
|
7:0 |
MSIO_AE_N |
RW |
0x0 |
MSIO input enable (active low) Value:
|
MSIO_APAD_MCU_OVR
- Name: MSIO Using MCU Domain Setting Control Register
- Description: This register controls MSIO using the settings from the MCU domain.
- Base Address: 0x4000A1E0
- Offset: 0x0
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:8 |
RSVD |
R |
N/A |
Reserved bits |
7:0 |
MSIO_MCU_OVR |
RW |
0x0 |
Use the settings from MCU domain, only valid when MCU domain is ON Value:
|
Electrical Specifications
The electrical parameters for the MSIO_0–MSIO_7 are as follows:
| Parameter | Description | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|
|
VIH |
Input high voltage |
VDDIO x 0.7 |
VDDIO |
V |
|
|
VIL |
Input low voltage |
VSSIO |
VDDIO x 0.3 |
V |
|
|
VOH,L |
Output high voltage, 2.5 mA, VDD ≥ 1.7 V |
VDD – 0.4 |
VDD |
V |
|
|
VOH,M |
Output high voltage, 2.5 mA, VDD ≥ 2.5 V |
VDD – 0.4 |
VDD |
V |
|
|
VOH,H |
Output high voltage, 2.5 mA, VDD ≥ 3 V |
VDD – 0.4 |
VDD |
V |
|
|
VOL,L |
Output low voltage, 2.5 mA, VDD ≥ 1.7 V |
VSS |
VSS + 0.4 |
V |
|
|
VOL,M |
Output low voltage, 2.5 mA, VDD ≥ 2.5 V |
VSS |
VSS + 0.4 |
V |
|
|
VOL,H |
Output low voltage, 2.5 mA, VDD ≥ 3 V |
VSS |
VSS + 0.4 |
V |
|
|
IOL |
Current at VSS+0.4 V, output set low, VDD ≥1.7 V |
7 |
mA |
||
|
IOH |
Current at VDD-0.4 V, output set high, VDD ≥ 1.7 V |
7 |
mA |
||
|
RPU |
Pull-up resistance |
70 |
120 |
150 |
kΩ |
|
RPD |
Pull-down resistance |
10 |
kΩ |
||
|
CPAD |
Pad capacitance |
10 |
pF |