Always-on Watchdog (AON_WDT)

Introduction

The Always-on Watchdog(AON_WDT) is a 32-bit countdown hardware timer. When the AON_WDT counter counts to 0, a system reset signal is sent, and when the counter value decreases to the set warning value, an interrupt signal is generated. Because the AON_WDT timer is in the AON domain, it can keep running when the MCU is off.

Main Features

The CLK register is a read/write register when the AON_WDT is disabled and is read only when the AON_WDT is enabled. Writing to the CLK register when the AON_WDT is enabled has no effect.
32-bit down counter running with a low-power clock
Generates an interrupt to warn the MCU when the 32-bit down counter reaches alarm values
16-bit alarm register, supporting reading and writing
Flexible clock source selections from LFRC_32K or LFXO_32K
An independent interrupt entry
Supports write access protection

Functional Description

The LOCK register enables or disables write accesses to all other registers. This is to prevent malicious software from disabling the watchdog functionality. Writing a value of 0x15CC5A51 (LOCK.LOCK_SET[31:1]) enables write accesses to all other registers. Writing any other value to the LOCK register disables the write accesses.
When the AON_WDT is disabled, all register values must be cleared to restore the default values.
When the CFG0.EN bit is set to 1, the value of the TIMER_W register is automatically loaded into the TIMER_R register, and the value starts to decrease.
The AON_WDT alarm interrupt is triggered when the value of the TIMER_R register decrements to the value of the ALARM_R register.
When the TIMER_R count value decrements to 0, the system restarts.

Block Diagram

The following figure shows the functional blocks of the Always-on watchdog module.

The watchdog starts running when AON_WDT_EN = 1 is synchronized to AON_WDT clock domain, which takes 1 – 3 RNG (Random Number Generators) clock cycles (20 – 100 µs).

If no reload operation is performed, the down counter default value is 0xFFFFFFFF. Otherwise, the counter will be reloaded with the value of timer_value.

Clock

The AON_WDT works in RNG clock (30 kHz – 50 kHz), which is much slower than MCU system clock (16 MHz – 64 MHz). Therefore, synchronization time is needed to propagate the MCU operations. For example, in reload operation, MCU needs to check whether the VAL_RD value has changed as expected.

Enable/Disable and Timer Reload

To enable the block, set AON_WDT_EN = 1 and wait until AON_WDT_RUNNING being high.
To disable the block, set AON_WDT_EN = 0 and wait until AON_WDT_RUNNING being low.
To reload down counter, program the desired value to timer_value, then set write-only register AON_WDT_RELOAD = 1. MCU can check read-only register VAL_RD to confirm.

Alarm

The AON_WDT provides an almost-expired alarm to warn MCU before system reset. By setting ALARM_VAL= N(non-zero), the AON_WDT generates an interrupt N RNG clocks before the system reset.

Registers

CFG_0

Name: CFG_0 Register
Description: This register sets AON_WDT configurations.
Base Address: 0x4000A700
Offset: 0x0
Reset Value: 0x00000000

Table 326 CFG_0 Register
Bits	Field Name	RW	Reset	Description
31:25	RSVD	R	0x0	Reserved bits
24	CFG	W	0x0	Writing 1 to this register triggers the watchdog timer configuration.
23:4	RSVD	R	0x0	Reserved bits
3	ALARM_SET	RW	0x0	Sets the timer alarm value.
2	ALARM_EN	RW	0x0	Enables AON WDT alarm.
1	RELOAD	W	0x0	Enables AON WDT timer reload (feed).
0	EN	RW	0x0	Enables AON WDT.

LOCK

Name: LOCK Register
Description: This register can prevent other registers of AON_WDT from being overwritten
Base Address: 0x4000A700
Offset: 0x4
Reset Value: 0x00000000

Table 327 LOCK Register
Bits	Field Name	RW	Reset	Description
31:1	LOCK_VALUE	W	–	Enable write access to all other registers by writing 0x15CC5A51. Disable write access by writing any other value to the LOCK register.
0	STATUS	R	0x0	0: Unlocked. Write to other watchdog registers is enabled. 1: Locked. Write to other watchdog registers is disabled.

STAT

Name: STAT Register
Description: This register can be used to get status of AON_WDT.
Base Address: 0x4000A700
Offset: 0x38
Reset Value: 0x00000000

Table 328 STAT Register
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R	0x0	Reserved bits
1	BUSY	R	0x0	Watchdog timer is busy. The application layer can perform other operations until this bit is set is 0.
0	STAT	R	0x0	AON WDT is running.

CLK

Name: CLK Register
Description: This register is used to select an AON_WDT clock source.
Base Address: 0x4000A700
Offset: 0x3C
Reset Value: 0x00000000

Table 329 CLK Register
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R	0x0	Reserved bits
1:0	CLK_SEL	RW	0x0	0x02: LFRC_32K (LFRC 32 kHz Clock) 0x03: LFXO_32K (LF_XO 32 kHz Clock)

TIMER_WR

Name: TIMER_WR Register
Description: This register is used to configure the initial AON_WDT value.
Base Address: 0x4000A700
Offset: 0x40
Reset Value: 0x00000000

Table 330 TIMER_WR Register
Bits	Field Name	RW	Reset	Description
31:0	TIMER_SET	RW	0x0	Write: Write the initial AON WDT value to the register. Read: Read the initial AON WDT value that users have configured. Read TIMER_RD to get the current internal value.

ALARM_WR

Name: ALARM_WR Register
Description: This register is used to configure the AON_WDT alarm value.
Base Address: 0x4000A700
Offset: 0x44
Reset Value: 0x64

Table 331 ALARM_WR Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R	0x0	Reserved bits
15:0	ALARM_SET	RW	0x64	Write: Write an AON WDT alarm value to the register. Read: Read the AON WDT alarm value that users have configured. Read ALARM_RD to get the current internal alarm value of AON WDT.

TIMER_RD

Name: TIMER_RD Register
Description: This register is used to get the current value of AON_WDT.
Base Address: 0x4000A700
Offset: 0x4C
Reset Value: 0x00000000

Table 332 TIMER_RD Register
Bits	Field Name	RW	Reset	Description
31:0	TIMER_RD	R	0x0	Current internal value of AON WDT

ALARM_RD

Name: ALARM_RD Register
Description: This register reads the current alarm value of AON_WDT.
Base Address: 0x4000A700
Offset: 0x50
Reset Value: 0x00000000

Table 333 ALARM_RD Register
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R	0x0	Reserved bits
15:0	ALARM_RD	R	0x0	Current internal alarm value of the AON WDT