Real-Time Counter (RTC/Calendar)

The Real-time Counter (RTC) modules provide a generic, low-power timer running on a low-frequency clock source. Since the RTC modules are in AON domain, the timer can keep running when the MCU is off. The modules can also wake up the system from Deep Sleep.

There are two identical RTC modules: one for calendar and the other for RTOS.

The RTC tick event interrupt module enables low power "tick-less" RTOS implementation as it optionally provides a regular interrupt source for an RTOS without the need to use the ARM® SysTick feature. Using the RTC tick event rather than the SysTick allows the CPU to be powered down while still keeping RTOS scheduling active.

Main Features

One ordinary compare interrupt
One tick event, supporting one-time counting and auto loading mode
32-bit up-counter register, supporting reading and writing
32-bit compare register, supporting reading and writing
32-bit down-tick register, supporting reading and writing
One clock divider, supporting NO_DIV, DIV_2, DIV_4, DIV_8, DIV_16, DIV_32, DIV_64, and DIV_128
Flexible clock source selections from LFRC_32K or LFXO_32K
An independent interrupt entry

Functional Description

The software has to enable RTC PMU LPD (RTC_EN) before using the RTC.
The CLK_DIV/CLK_SEL register is a read/write register when the RTC is disabled and is read only when the RTC is enabled. Writing to the CLK_DIV/CLK_SEL register when the RTC is started has no effect.
The OVERFLOW, COMPARE, and tick event interrupts are enabled by default.
When RTC is enabled, the TIMER_RD register starts to count. When users set the values of the TIMER_SET register and TIME_SET bit to 1, the calendar module synchronizes the count value to the TIMER_RD register and starts timing.
When RTC is disabled, all register values must be cleared to the default values.
When the value of the TIMER_RD register is equal to that of the CMP_RD register, the ordinary compare interrupt is triggered.
RTC tick event interrupt register is a value-decreasing register. When the auto reloading mode is set (TICK_TYPE), the value of the counter (TICK_SET) is automatically reloaded (TICK_RD) when the interrupt is triggered.
When the count value of the TIMER_RD register overflows, the overflow interrupt is triggered, and the TIMER_RD register continues counting from 0.

Registers

CTRL

Name: CTRL Register
Description: This register sets RTC configurations.
Base Address: 0x4000A600 + x*0x80
Offset: 0x00
Reset Value: 0x00000000

Table 334 CTRL Register
Bits	Field Name	RW	Reset	Description
31:25	RSVD	R	0x0	Reserved bits
24	CFG	RW	0x0	Writing 1 to this register triggers the calendar timer configuration.
23:11	RSVD	R	0x	Reserved bits
10	TICK_TYPE	RW	0x0	Sets the RTC tick event mode. 0x0: One-time 0x1: Auto reloading
9	TICK_SET	RW	0x0	Sets the RTC tick event timer value.
8	TICK_EN	RW	0x0	Enables RTC tick event.
7:5	RSVD	R	0x0	Reserved bits
4	WRAP_CLR	RW	0x0	Clears wrap counter.
3	CMP_SET	RW	0x0	Sets the RTC COMPARE timer value.
2	COMPARE_EN	RW	0x0	Enables RTC COMPARE timer.
1	TIME_SET	RW	0x0	Sets the RTC initial timer value.
0	EN	RW	0x0	Enables RTC timer.

CLK_DIV

Name: CLK_DIV Register
Description: This register is used to set the frequency division coefficient
Base Address: 0x4000A600 + x*0x80
Offset: 0x4
Reset Value: 0x00000000

Table 335 CLK_DIV Register
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R	0x0	Reserved bits
2:0	CLK_DIV	RW	0x0	0x0: NO_DIV. Not divided. Counting at SLP_CLK 0x1: DIV_2. Counting at 1/2 of SLP_CLK 0x2: DIV_4. Counting at 1/4 of SLP_CLK 0x3: DIV_8. Counting at 1/8 of SLP_CLK 0x4: DIV_16. Counting at 1/16 of SLP_CLK 0x5: DIV_32. Counting at 1/32 of SLP_CLK 0x6: DIV_64. Counting at 1/64 of SLP_CLK 0x7: DIV_128. Counting at 1/128 of SLP_CLK

IRQ_EN

Name: IRQ_EN Register
Description: This register is used to enable RTC interrupts.
Base Address: 0x4000A600 + x*0x80
Offset: 0x14
Reset Value: 0x00000007

Table 336 IRQ_EN Register
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R	0x0	Reserved bits
2	TICK_EVT	RW	0x1	RTC tick event interrupt. Write 1 to enable the interrupt.
1	OVERFLOW	RW	0x1	RTC overflow interrupt. Write 1 to enable the interrupt.
0	COMPARE	RW	0x1	RTC COMPARE interrupt. Write 1 to enable the interrupt.

IRQ_STAT

Name: IRQ_STAT Register
Description: This register is used to get interrupt status of the RTC.
Base Address: 0x4000A600 + x*0x80
Offset: 0x18
Reset Value: 0x00000000

Table 337 IRQ_STAT Register
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R	0x0	Reserved bits
2	TICK_EVT	RW	0x0	RTC tick event interrupt. Write 1 to clear the interrupt.
1	OVERFLOW	RW	0x0	RTC overflow interrupt. Write 1 to clear the interrupt.
0	COMPARE	RW	0x0	RTC COMPARE interrupt. Write 1 to clear the interrupt.

STAT

Name: STAT Register
Description: This register is used to get the RTC status.
Base Address: 0x4000A600 + x*0x80
Offset: 0x38
Reset Value: 0x00000000

Table 338 STAT Register
Bits	Field Name	RW	Reset	Description
31:12	RSVD	R	0x0	Reserved bits
11:8	WRAP_CNT	R	0x0	Calendar timer wrap-around counter
7:5	RSVD	R		Reserved bits
4	BUSY	R	0x0	Calendar timer is busy. The application layer can perform other operations until this bit is set is 0.
3:1	RSVD	R		Reserved bits
0	STAT	R	0x0	RTC timer is running.

CLK_SEL

Name: CLK_SEL Register
Description: This register is used to select a clock source.
Base Address: 0x4000A600 + x*0x80
Offset: 0x3C
Reset Value: 0x00000000

Table 339 CLK_SEL Register
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R	0x0	Reserved bits
1:0	CLK_SEL	RW	0x0	0x02: LFRC_32K (LFRC 32 kHz Clock) 0x03: LFXO_32K (LF_XO 32 kHz Clock)

CMP_SET

Name: CMP_SET Register
Description: This register is used to set the COMPARE timer value.
Base Address: 0x4000A600 + x*0x80
Offset: 0x40
Reset Value: 0x00000000

Table 340 CMP_SET Register
Bits	Field Name	RW	Reset	Description
31:0	CMP_SET	RW	0x0	Write: RTC COMPARE timer value to configure Read: The value you just set. Read CMP_RD to get the current internal value.

TIMER_SET

Name: TIMER_SET Register
Description: This register is used to set the RTC timer value.
Base Address: 0x4000A600 + x*0x80
Offset: 0x44
Reset Value: 0x00000000

Table 341 TIMER_SET Register
Bits	Field Name	RW	Reset	Description
31:0	TIMER_SET	RW	0x0	Write: RTC timer value to configure Read: The value you just set. Read TIMER_RD to get the current internal value.

TICK_SET

Name: TICK_SET Register
Description: This register is used to set the tick event timer value
Base Address: 0x4000A600 + x*0x80
Offset: 0x48
Reset Value: 0x00000000

Table 342 TICK_SET Register
Bits	Field Name	RW	Reset	Description
31:0	TICK_SET	RW	0x0	Write: RTC tick event timer value to configure Read: The value you just set. Read TICK_RD to get the current internal value.

TIMER_RD

Name: TIMER_RD Register
Description: This register is used to get the internal value of the RTC timer.
Base Address: 0x4000A600 + x*0x80
Offset: 0x50
Reset Value: 0x00000000

Table 343 TIMER_RD Register
Bits	Field Name	RW	Reset	Description
31:0	TIMER_RD	R	0x0	Current internal value of the RTC timer

CMP_RD

Name: CMP_RD Register
Description: This register is used to get the value of the RTC COMPARE timer.
Base Address: 0x4000A600 + x*0x80
Offset: 0x54
Reset Value: 0x00000000

Table 344 CMP_RD Register
Bits	Field Name	RW	Reset	Description
31:0	CMP_RD	R	0x0	Current internal value of the RTC COMPARE timer

TICK_RD

Name: TICK_RD Register
Description: This register used to get the value of the RTC tick event timer.
Base Address: 0x4000A600 + x*0x80
Offset: 0x58
Reset Value: 0x00000000

Table 345 TICK_RD Register
Bits	Field Name	RW	Reset	Description
31:0	TICK_RD	RW	0x0	Current internal value of the RTC tick event timer.