Digital Dynamic Voltage Scaling (DDVS)

Introduction

The performance of CMOS circuits is affected by PVT (Process, Voltage, Temperature) deviations. In the case of fixed P/T, Speed and Voltage are positively correlated within the allowable range of work. The dynamic power consumption of the circuit is positively related to the square of frequency and voltage:

Digital Dynamic Voltage Scaling (DDVS) uses the correlation between voltage, delay and power consumption to dynamically adjust the voltage of the CORE_LDO to achieve a balance and optimization of performance and power consumption on chips with different process variations.

Main Features

Automatic mode and manual mode
Ringo output frequency division
Up to four Ringo inputs
Supporting generating or masking error interrupt

Functional Description

Architecture

As shown in the figure below, DDVS supports up to four Ringo inputs. Each Ringo input is first counted according to the reference clock. Then the count results are compared with the lookup table (LUT) written by MCU in advance. Finally, the appropriate voltage value is obtained by calculation, and the voltage of the CORE_LDO is adjusted through the PMU. Since the clock of the APB is asynchronous to the reference clock used inside the DDVS module, DDVS will perform clock synchronization processing.

Programming

DDVS can be enabled or disabled by configuring the DDVS_EN.DDVS_EN bit.

DDVS supports two working modes: automatic mode and manual mode, which can be configured through the DDVS_CFG_1.CONF_DDVS_MODE bit.

Automatic mode

In automatic mode, the MCU finds the upper limit value in the lookup table which is generated from testing and estimation, and writes the value into the CONF_TARGET_CNT field in the DDVS_CFG_2 register of the module.

After the DDVS module is enabled, according to the current value of each Ringo, the voltage of CORE_LDO is automatically adjusted until the target is reached.

When the chip speed is higher than the target, DDVS will reduce the voltage until it meets the performance requirements and LOCK to reduce power consumption.
When the chip speed is lower than the target, DDVS will increase the voltage until it meets the performance requirements and LOCK.

When the voltage drops to the lowest level, DDVS will stop the adjustment and LOCK. When the voltage rises to the highest gear and still fails to meet the target, DDVS will stop the adjustment and report an exception. The interrupt is controlled by the DDVS_CFG_1.CONF_INT_EN bit. The IRQ of DDVS error is #27 DDVS_ERR_IRQ.

When the speed exceeds the high threshold in LOCK mode, DDVS will re-enter the adjustment mode and increase the voltage. The high threshold can be configured through the field DDVS_CFG_2.CONF_THRESHOLD_FAST.

When the speed is lower than the slow threshold in LOCK mode, DDVS will re-enter the adjustment mode and decrease the voltage. The low threshold can be configured through the field DDVS_CFG_1.CONF_THRESHOLD_SLOW.

Manual mode

In manual mode, the MCU adjusts the voltage by reading the real-time value of each Ringo and judging by the software algorithm. Usually, developers need to manually adjust the voltage of CORE_LDO, and then compare the Ringo count value obtained by DDVS with the expected value to determine whether the current voltage of CORE_LDO is appropriate. The larger of the Ringo counter value, the slower the system so that the voltage of CORE_LDO should be increased.

Each Ringo can be enabled separately through the field DDVS_CFG_1.CONF_RINGO_EN . When multiple Ringos are sampled at the same time, if the value of each counter is different, the maximum value is suitable for the calculation.

DDVS supports configuring the output frequency range of the Ringo counter through the field DDVS_CFG_1.CONF_DIV_FACTOR to avoid that Ringo counter value overflowing or being too small. When the DDVS error interrupt is enabled, the DDVS error interrupt can be cleared only through the DDVS_CFG_1.ERR_INT bit in manual mode. The current state of DDVS can be checked by the DDVS_FSM register.

Note: