Clock Gating
Architecture
Clock gating is a power management technique used in many digital designs for reducing dynamic power dissipation, by removing the clock signal when the circuit is not in use or ignores clock signal. Clock gating saves power by pruning the clock tree, at the cost of adding more logic to a circuit. When not being switched, the switching power consumption goes to zero, and only leakage currents are incurred.
In the SoC, a lot of clock gates (CG) are implemented, as shown in the figure below, in order to optimize power consumption. Clock gating supports mandatory control and dynamic control of the clock through software. Clock gates are divided according to functional categories, accurate to each system or peripheral module. Through the finely divided clock gates, developers can implement subtle digital circuit power control, thereby reducing the overall power consumption of the chip.
The peripheral driver in the SDK has implemented that the corresponding clock is automatically turned on through CGs. Through the initialization API in the SDK, developers do not need to manually open the module clock.
The CG control management in sleep mode has been implemented in the SDK. Because the peripheral control registers are not in the AON power domain, the configuration will be lost after entering sleep mode so that the critical register configuration should have been backed up before sleep. The clocks will be turned on through the CGs during the wake-up phase, and the critical register configuration will be restored automatically.
Programming
The clock of the system or peripheral module can be controlled by the CGs. The CGs can be configured into mandatory control mode or dynamic control mode, which improves the flexibility of power controlling.
The clocks of each module can be forced off by configuring the MCU_SUBSYS_CG_CTRL[1], MCU_SUBSYS_CG_CTRL[2], MCU_PERIPH_PCLK_OFF, SECU_CLK_CTRL and MCU_MISC_CLK registers.
Some of the modules support dynamic control during WFI/WFE. By configuring the MCU_SUBSYS_CG_CTRL[0], MCU_SUBSYS_CG_CTRL[2], MCU_PERIPH_CLK_SLP_OFF and SECU_CLK_CTRL registers, the clock of the module can be automatically turned off in CPU sleep mode. If the current clock gating of the module is forced off, the dynamic control will not take effect.
Developers is able to control the clock of each module through the CG register described in "Registers".
