True Random Number Generator (TRNG)

表 487 TRNG module standard

Document Code	Name of Standard
NIST SP 800-22	A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications

The location of RNG module in the system is shown in figure below. Digital_FRO is the digital true random number generator, based on the FRO scheme. Post-process logic is added in RNG module to ensure the quality of random number and amend the bias of true random number generator (TRNG).

The TRNG module supports pseudo random number generation and true random number generation. Pseudo random numbers are generated by a linear feedback shift register (LFSR). True random numbers are generated by using a feedforward ring oscillator(FRO) as the entropy source.

The work mode of the LFSR can be configured as 128 or 59 polynomial which is implemented by Galois structure. The LFSR seed can be configured from the FRO or in parallel be written in user-configured seed by using the USER_SEED register.

The TRNG module supports multiple output modes, including LFSR direct output, LFSR XOR TRNG, LFSR and TRNG cyclic sampling, LFSR and TRNG cyclic sampling and parity generation, and the FRO direct output. Since only the FRO is used as the true random number source, the results of LFSR direct output, LFSR XOR TRNG, as well as LFSR and TRNG cyclic sampling will be the same when the LFSR seed is configured by users.

The TRNG module supports multiple post-processing mechanisms, including bit-skipping, bit-counting and Von-Neumann corrector.

• bit-skipping: Select 1-bit for every 5-bit as the final output.
• bit-counting: XOR every 5-bit into 1-bit as the final output.
• Von-Neumann corrector: Judge two consecutive bits and output 1-bit with the rules that skipping if the 2-bit is 00B or 11B, output as 0B if the 2-bit is 01B, output as 1B if the 2-bit is 10B.

The CONFIG register can be used to configure relevant parameters for the TRNG module. CONFIG.OUT_MODE can be used to configure the output mode. CONFIG.POST_MODE can be used to configure the post-process mode. CONFIG. LFSR_MODE can be used to configure the 59-bit or 128-bit LFSR operation mode. CONFIG.LFSR_SEED_SEL can be used to configure the LFSR seed source. CONFIG.IRQ_EN can set the TRNG module into interrupt mode.

The FRO acts as the entropy source so that CONFIG.FRO_EN should be enabled in order to generate true random numbers. It can directly output or be set as the LFSR seed.

The TRNG module also supports user-defined LFSR seeds. In the 59-bit LFSR operation mode, the USER_SEED register needs to be written 4 consecutive times to configure the seed. In the 128-bit LFSR operation mode, the USER_SEED register needs to be written 8 consecutive times to configure the seed. If the output mode is set to LFSR directly output, the random number will be pseudo random number.

he TRNG module can be started by using the CTRL register. The STAT register is used to indicate the current status of the TRNG module. The generated random number can be read out from the DATA register.

• Name: TRNG Controller Register

• Description: This register acts as a global enable/disable for TRNG.

• Base Address: 0x40019000

• Offset: 0x0

• Reset Value: 0x00000000

表 488 TRNG Controller Register

Bits	Field Name	Access	Reset Value	Description
31:1	RSVD	R		Reserved bits
0	RUN_EN	RW	0x0	TRNG working enable signal, valid at HIGH 0x0: Disable TRNG module. 0x1: TRNG starts working to execute an operation of reading random number.

• Name: TRNG Status Register

• Description: This is a read-only register used to indicate the current status of TRNG.

• Base Address: 0x40019000

• Offset: 0x4

• Reset Value: 0x00000000

表 489 TRNG Status Register

Bits	Field Name	Access	Reset Value	Description
31:1	RSVD	R		Reserved bits
0	READY	R WC	0x0	TRNG status flag bit, queried by CPU. Value: 0x0: TRNG output data is not valid. 0x1: TRNG output data is valid. This register is automatically cleared by hardware after READY is set HIGH. This register is automatically cleared by hardware after data reads.

• Name: TRNG Data Register

• Description: This register is a 32-bit read buffer for the random numbers.

• Base Address: 0x40019000

• Offset: 0x8

• Reset Value: 0x00000000

表 490 TRNG Data Register

Bits	Field Name	Access	Reset Value	Description
31:0	VALUE	R	0x0	TRNG data. This register is automatically cleared by hardware after data reads.

• Name: TRNG Long Run Status Register

• Description: This is a read-only register used to indicate the current status of long run mode.

• Base Address: 0x40019000

• Offset: 0x10

• Reset Value: 0x00000000

表 491 TRNG Long Run Status Register

Bits	Field Name	Access	Reset Value	Description
31:9	RSVD	R		Reserved bits
8:1	CNT	R	0x0	Counts of TRNG long run test. This value is incremented by 1 for every long run detected by TRNG. After TRNG is disabled or reset, the register is cleared.
0	LFLAG	R	0x0	Flag of TRNG long run test Value: 0x0: Long run never occurs. 0x1: Long run was occurred in random number sequence After TRNG is disabled or reset, this register is cleared.

• Name: TRNG Configuration Register

• Description: This register acts as a configuration for TRNG.

• Base Address: 0x40019000

• Offset: 0x14

• Reset Value: 0x0000B246

表 492 TRNG Configuration Register

Bits	Field Name	Access	Reset Value	Description
31:16	RSVD	R		Reserved bits
15	FRO_EN	RW	0x1	Ring oscillator TRNG enable signal Value: 0x0: Disabled 0x1: Enabled
14	LFS_EN	RW	0x0	Low frequency sampling TRNG enable signal Value: 0x0: Disabled 0x1: Enabled Reserved.
13	IRQ_EN	RW	0x1	TRNG hardware interrupt enable bit. Active high.
12:10	LFSR_SEED_SEL	RW	0x4	LFSR seed configuration mode. Select a source for LFSR seed. Value: 0x0: LFSR seed is from the switching current s0 0x1: LFSR seed is from the switching current s1 0x2: LFSR seed is from the switching current s2 0x3: LFSR seed is from the switching current s3 0x4: LFSR seed is from the oscillator s0 0x5: LFSR seed is from the Low Frequency Sampling s0 0x6: LFSR seed is configured by users 0x7: Random numbers do not use LFSR and completely use true random mode. Value is limited to 0x4 or 0x6 in the device.
9	LFSR_MODE	RW	0x1	LFSR configuration mode: 0x0: 59-bit LFSR 0x1: 128-bit LFSR
8:7	POST_MODE	RW	0x0	TRNG post-process configuration Value: 0x0: No post-process 0x1: Bit skipping 0x2: Bit counting 0x3: Von-Neumann
6:4	LFSR_XOR_SEL	RW	0x4	In Output mode 8, select TRNG with LFSR XOR 0x4: LFSR Ring Oscillator s0 Note: means XOR. Value is limited to 0x4 in the device.
3:0	OUT_MODE	RW	0x6	Select a TRNG output mode Value: 0x4: Digital TRNG direct output, ring oscillator s0 0x6: LFSR and TRNG cyclic sampling and parity generation 0x7: LFSR and TRNG cyclic sampling 0x8: LFSR TRNG 0x9: LFSR direct output Note: means XOR. Value is limited to 0x4, 0x6, 0x7, 0x8, or 0x9 in the device.

• Name: TRNG Source Configuration Register

• Description: This register acts as a configuration for source of TRNG.

• Base Address: 0x40019000

• Offset: 0x18

• Reset Value: 0x00007864

表 493 TRNG Source Configuration Register

Bits	Field Name	Access	Reset Value	Description
31:15	RSVD	R		Reserved bits
14:11	FRO_CHAIN	RW	0xF	Selection of Chain4–Chain7 for FRO Value: 0x0: Select long ring. 0x1: Select short ring.
10:8	RSVD	R		Reserved bits
7:0	TRDY_TIME	RW	0x64	The waiting time during which the TRNG input reaches stable. Default value is 100 time cycles.

• Name: TRNG FRO Configuration Register

• Description: This register acts as a configuration for FRO.

• Base Address: 0x40019000

• Offset: 0x1C

• Reset Value: 0x0000FFFF

表 494 TRNG FRO Configuration Register

Bits	Field Name	Access	Reset Value	Description
31:16	RSVD	R		Reserved bits
15:8	TEST_IN	RW	0xFF	Test input signal of each chain for FRO. The default value is 1.
7:0	CHAIN_EN	RW	0xFF	Enable signal of each chain in ring oscillator module. It is valid when FROEN is high.

• Name: TRNG User Seed Register

• Description: This register acts as a user seed value for TRNG.

• Base Address: 0x40019000

• Offset: 0x20

• Reset Value: 0x00000000

表 495 TRNG User Seed Register

Bits	Name	Access	Reset Value	Description
31:16	RSVD	R		Reserved bits
15:0	USER_SEED	W	0x0	RNG seed configured by users. Write four times to user_seed[58:0] to configure a 59-bit random number. Write eight times to user_seed[127:0] to configure a 128-bit random number.

• Name: TRNG Long Run Configuration Register

• Description: This register acts as a configuration for long run mode.

• Base Address: 0x40019000

• Offset: 0x24

• Reset Value: 0x00000035

表 496 TRNG Long Run Configuration Register

Bits	Field Name	Access	Reset Value	Description
31:6	RSVD	R		Reserved bits
5:1	TEST_LIMIT	RW	0x1A	Threshold configuration of RNG long run test. The run which lasts in a longer or an equal period than this value will be detected. Default value is 26 and the maximum value is 31.
0	TEST_EN	RW	0x1	RNG long run test enable bit Value: 0x0: Disabled 0x1: Enabled