Functional Overview
A reset is triggered by power, hardware or software in the SoC. Power reset includes power-on reset and brown- out reset. Hardware reset includes external reset pin (CHIP_EN) and watchdog reset. Software reset refers to the NVIC System Reset Register (AIRCR) as defined in Cortex®-M4.
The reset structure of this SoC is illustrated in the figure below.
The PMU, triggered by CHIP_EN pad, POR circuit or BOD reset circuit, generates an active low por_rst_n reset signal. The watchdog reset by the watchdog timer in the always-on power domain generates an active low aon_wdog_rst_n reset signal. Either of these two reset signals will cause an active low pwr_rst_n reset signal to the power state controller, resulting in generating a reset signal of the SoC.
The power state controller generates an active low MCU Core Reset (mcu_core_rst_n), which goes directly to Cortex®-M4F core reset input. In order to support CPU-initiated system reset, the System Reset Request output of Cortex®-M4F is combined with mcu_core_rst_n, and the resulting System Reset (sys_rst_n) is connected to MCU peripherals as well as the XF Cache and always-on peripherals.
The reset sources are illustrated as below:
| Reset Source | POR | BOD | Watchdog | SYSRESETREQ |
|---|---|---|---|---|
| Power state controller | Impacted | Impacted | Impacted | Not impacted |
| Always-on power control | Impacted | Impacted | Impacted | Not impacted |
| Always-on peripherals | Impacted | Impacted | Impacted | Impacted |
| Always-on memory control | Impacted | Impacted | Impacted | Impacted |
| Always-on others | Impacted | Impacted | Impacted | Impacted |
| Bluetooth LE timer | Impacted | Impacted | Impacted | Impacted |
| Bluetooth LE core | Impacted | Impacted | Impacted | Impacted |
| MCU subsystem | Impacted | Impacted | Impacted | Impacted |
| Cortex®-M4 core | Impacted | Impacted | Impacted | Impacted |
| Cortex®-M4 debug | Impacted | Impacted | Impacted | Not impacted |
