Clock Mapping on Pin
Introduction
Clocks can be mapped to external pins by configuration. This function allows developers to obtain the internal clock frequency of the chip. In specific occasions, developers can customize the clock calibration scheme through the clock drawn from the pins.
Main Features
- Mapping divided HFXO_32M to a pin
- Mapping divided CPLL_192M to a pin
- Mapping divided HFRC_192M to a pin
- Mapping LFXO_32K to a pin
- Mapping RNG_32K and RNG_OSC to a pin
- Mapping LFRC_32K to a pin
Programming
The low frequency clocks (such as RNG_32K, RNG_OSC, LFRC_32K, and LFXO_32K) generated from analog circuit can be mapped to the AON_GPIO_4 pin.
The mapping can be achieved with software by:
- Configure the field AON_PAD_CLK. AON_GPIO4_CLK__SEL to select the mapped clock.
- Configure the AON_PAD_CLK. AON_GPIO4_OUT_EN bit to enable the clock output via the AON_GPIO_4 pin.
| Clock | AON_PAD_CLK.AON_GPIO4_CLK__SEL |
|---|---|
| RNG_32K | 0x0 |
| RNG_OSC | 0x1 |
| LFRC_32K | 0x2 |
| LFXO_32K | 0x3 |
Due to its high frequency, it is recommended to observe HFXO_32M by mapping HFXO_2M (generated by dividing HFXO_32M by 16) to the AON_GPIO_5 pin in an analog circuit. The mapping can be achieved with software by:
- Setting the XO_CTRL.2MHZ_ENA bit to enable HFXO_2M from RF (enabled by default).
- Setting the XO_CTRL.2MHZ_OUT bit to enable the clock output via the AON_GPIO_5 pin.
Both CPLL_192M and HFRC_192M can be mapped to arbitrary pins through the test bus. Due to the high frequency of the clocks, the mapped clock is divided by 12 to 16 MHz. The mapping can be achieved with software by:
- Select the current 192 MHz clock source through the AON_CLK register.
- Configure the TESTBUS_CTRL register (TESTBUS_CTRL = 0x0006C002).
- Configure the IO to mux on TEST_BUS (PIN MUX = 55).
