Memory Map
Based on the storage architecture of the Cortex®-M4F processor, this SoC divides its memory into ROM, Flash, data memory, peripheral memory, and memory for debugging components. Taking a GR5332 SoC as an example, all the mapping spaces of the 4 GB SoC memory are shown in 图 6.
-
The contents of the ROM area have been preprogrammed and cannot be modified by developers. This area mainly stores the startup process and code related to Bluetooth LE protocol stack.
-
The RAM Alias area is used to store special-purpose code segments that are generally used for Flash operations or to speed up code fetching. Due to the characteristics of the Cortex®-M4F bus architecture, there are independent instruction bus (I-CODE) and data bus (D-CODE) in the address space of 0x0000 0000–0x1FFF FFFF. The two buses can be used to fetch instructions and data in parallel. However, in the address space of 0x2000 0000–0xDFFF FFFF, there is only one system bus (System) available which allows for fetching instructions and data serially. Therefore, it is more efficient to allocate code segments and constants in the area of 0x0000 0000–0x1FFF FFFF.
-
The ExFlash area is generally used to store user code.
-
The RAM area is generally used to store data and code copied from Flash. In the Arm® Cortex®-M4F architecture, the RAM Bit Banding in the area of 0x2200 0000–0x2227 FFFF are conducive to the atomic characteristics of data operations.
-
The peripheral memory is mapped into the Peripheral area within the address space of 0x40000000–0x400FFFFF. The Peripheral Bit Banding area, which is located in the area of 0x42000000–0x43FFFFFF, is generally used for supporting bit-band operations.
-
The ARM Private area is generally used for private peripheral bus debugging and private peripheral bus in the area of 0xE0000000-0xE00FFFFF.
