SRAM Power Control
The main Static Random Access Memory (SRAM) is comprised of an on-chip static RAM totaling up to 96 KB. The SRAM is implemented as multiple SRAM instances for greater control over power usage when less SRAM is required (6 x 16 KB instances).
The SRAM consists of peripheral circuits and bit arrays, and is powered by VDD and VDM separately, as shown in the figure below.
To reduce the power consumption of the SRAM during sleep, developers can turn off the unused SRAM instances or set active SRAM instances to be retained (neither reading nor writing are allowed).
Power Mode
Three SRAM power modes are available:
- Full power
SRAM can provide full-speed read/write function. This mode is only used when the MCU is powered on.
- Retention power
When the system enters sleep mode, the SRAM can enter the retention state, allowing data to be retained. Neither read nor write operations are available in this mode.
- Power off
In this mode, all data will be cleared, and the SRAM will enter power-down state. If users need to control the power supply of SRAM, it is recommended to use the standard functions in the SDK which provides functions for automatic management of SRAM. This function will be automatically managed according to the RAM used by the user programs.
Power Domain
There are six power domains for the SRAM, from pd_mcu_00 to pd_mcu_05. The relationship between the SRAM instances and the power domains is shown as follows.
| Instance | Access Offset | Size (KB) | Power Domain | Cell Size (KB) | |
|---|---|---|---|---|---|
| Low | High | ||||
SRAM0 |
0x00000000 |
0x00007FFF |
16 |
pd_mcu_00 |
16 |
SRAM1 |
0x00008000 |
0x0000FFFF |
16 |
pd_mcu_01 |
16 |
SRAM2 |
0x00010000 |
0x00017FFF |
16 |
pd_mcu_02 |
16 |
SRAM3 |
0x00018000 |
0x0001FFFF |
16 |
pd_mcu_03 |
16 |
SRAM4 |
0x00020000 |
0x00027FFF |
16 |
pd_mcu_04 |
16 |
SRAM5 |
0x00028000 |
0x0002FFFF |
16 |
pd_mcu_05 |
16 |
Programming
The SRAM power domain in the wake-up phase can be set through the MEM_PWR_WKUP0 register. The SRAM power domain in sleep mode can be configured by the MEM_PWR_APPLY.APPLY bit which is used to apply the configuration of MEM_PWR_WKUP0 or MEM_PWR_SLP0. The current operating state of the SRAM power domain can be obtained by reading from the MEM_PWR_STAT0 register. However, the reading operation is not allowed when the MEM_PWR_APPLY field is busy.
Because the SRAM instances and the power domains do not correspond one-to-one, developers need to configure specific registers according to their relationship shown in the table below.
| Instance | MEM_PWR_SLP0 | MEM_PWR_WKUP0 | MEM_PWR_STAT0 |
|---|---|---|---|
SRAM0 |
SET00[1:0] |
SET00[1:0] |
SET00[1:0] |
SRAM1 |
SET01[3:2] |
SET01[3:2] |
SET01[3:2] |
SRAM2 |
SET02[5:4] |
SET02[5:4] |
SET02[5:4] |
SRAM3 |
SET03[7:6] |
SET03[7:6] |
SET03[7:6] |
SRAM4 |
SET04[9:8] |
SET04[9:8] |
SET04[9:8] |
SRAM5 |
SET05[11:10] |
SET05[11:10] |
SET05[11:10] |
Typically, the first 8 KB of the SRAM0 instance is reserved for the Bootloader and Bluetooth LE protocol stack. Therefore, pd_mcu_00 should be set to be full power during the wakeup phase, and it should be set to retention mode in sleep mode.
For detailed instructions on usage of SRAM, refer to GR533x Developer Guide.
