Functional Description

The device supports DMA as flow controller only. There are four transfer types:

• Memory to memory
• Memory to peripheral
• Peripheral to memory
• Peripheral to peripheral

For memory, the source transfer width must be less than or equal to the data bus width of AHB master interface, normally 8, 16, or 32 bits. For a non-memory, the source transfer width is equal to the peripheral FIFO width.

For memory, the destination transfer width must be less than or equal to the data bus width of AHB master interface, normally 8, 16, or 32 bits. For a non-memory, the destination transfer width is equal to the peripheral FIFO width.

• Source address increment: It indicates whether to increase, decrease, or remain the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address, then set this field to No change.
• Destination address increment: This decides whether to increase, decrease, or remain the destination address on every source transfer. If the device is fetching data from a destination peripheral FIFO with a fixed address, then set this field to No change.

Each channel has a programmable priority in the range of 0–5, from lowest to highest. Channel priority applies to most scenarios except those on master bus. It is worth noting that a request for the master bus interface can be made at any time, but the request is granted only after the current AHB transfer (burst or single) completes. Therefore, when the master interface is transferring data for a low-priority channel while a high priority channel requests service, it completes the current AHB transfer (burst or single) for the low-priority channel before switching to data transfer for the high one.

DMA has five channels in total; each channel has a FIFO and is independent from each other. The FIFO of each channel is 32-bit wide. After the DMA channel is enabled, the DMA obtains data from the source according to the bit width configured for the source and stores the data into the DMA FIFO.

The DMA takes out the data from the DMA FIFO according to the bit width configured for the target and sends the data to the destination. Regardless of the configured transmission bit width, the data obtained from the source is compactly stored (this helps maximize the use of DAM FIFO storage space).

For example, the transmission bit width is 16 bits, and the FIFO bit width is 32 bits, so one depth of DMA FIFO will store two 16-bit data entries. It is worth mentioning that when DMA is used as flow control, the total number of bytes (blk_size_bytes_dma) transmitted by DMA in a single transmission depends on the product of the source transmission bit width (src_single_size_bytes) and the block size (CTL_HIx.BLOCK_TS). The detailed calculation methods are as follows:

表 515 Transfer operations by source/destination bit width in DMA transfer

Source Interface Width	Destination Interface Width	Block Size (DMA as Flow Control)	Source Content: Address/Data	Transfer Operations	Destination Content: Address/Data
8	8	4	@0x0/B0 @0x1/B1 @0x2/B2 @0x3/B3	1: READ B0[7:0] @0x0 To DMA then WRITE B0[7:0] @0x0 2 :READ B1[7:0] @0x1 To DMA then WRITE B1[7:0] @0x1 3: READ B2[7:0] @0x2 To DMA then WRITE B2[7:0] @0x2 4: READ B3[7:0] @0x3 To DMA then WRITE B3[7:0] @0x3	@0x0/B0 @0x1/B1 @0x2/B2 @0x3/B3
8	16	4	@0x0/B0 @0x1/B1 @0x2/B2 @0x3/B3	1 :READ B0[7:0] @0x0 To DMA 2: READ B1[7:0] @0x1 To DMA then WRITE B1B0[15:0] @0x0 3: READ B2[7:0] @0x2 To DMA 4: READ B3[7:0] @0x3 To DMA then WRITE B3B2[15:0] @0x2	@0x0/B1B0 @0x2/B3B2
8	32	4	@0x0/B0 @0x1/B1 @0x2/B2 @0x3/B3	1: READ B0[7:0] @0x0 To DMA 2: READ B1[7:0] @0x1 To DMA 3: READ B2[7:0] @0x2 To DMA 4: READ B3[7:0] @0x3 To DMA then WRITE B3B2B1B0[32:0] @0x0	@0x0/B3B2B1B0
16	8	2	@0x0/B1B0 @0x2/B3B2	1: READ B1B0[15:0] @0x0 To DMA then WRITE B0[7:0] @0x0 2: WRITE B1[7:0] @0x1 3: READ B3B2[15:0] @0x2 To DMA then WRITE B2[7:0] @0x2 4: WRITE B3[7:0] @0x3	@0x0/B0 @0x1/B1 @0x2/B2 @0x3/B3
16	16	2	@0x0/B1B0 @0x2/B3B2	1: READ B1B0[15:0] @0x0 To DMA then WRITE B1B0[15:0] @0x0 2: READ B3B2[15:0] @0x2 To DMA then WRITE B3B2[15:0] @0x2	@0x0/B1B0 @0x2/B3B2
16	32	2	@0x0/B1B0 @0x2/B3B2	1: READ B1B0[15:0] @0x0 To DMA 2: READ B3B2[15:0] @0x2 To DMA then WRITE B3B2B1B0[32:0] @0x0	@0x0/B3B2B1B0
32	8	1	@0x0/B3B2B1B0	1: READ B3B2B1B0[32:0] @0x0 To DMA then WRITE B0[7:0] @0x0 2: WRITE B1[7:0] @0x1 3: WRITE B2[7:0] @0x2 4: WRITE B3[7:0] @0x3	@0x0/B0 @0x1/B1 @0x2/B2 @0x3/B3
32	16	1	@0x0/B3B2B1B0	1: READ B3B2B1B0[32:0] @0x0 To DMA then INTWRITE B1B0[15:0] @0x0 2: WRITE B3B2[15:0] @0x2	@0x0/B1B0 @0x2/B3B2
32	32	1	@0x0/B3B2B1B0	1: READ B3B2B1B0[32:0] @0x0 To DMA then WRITE B3B2B1B0[32:0] @0x0	@0x0/B3B2B1B0

For each channel, there are three types of interrupt sources:

• IntTfr: DMA Transfer Complete Interrupt
• IntBlock: Block Transfer Complete Interrupt. This interrupt is generated on DMA block transfer completion to the destination peripheral.
• IntErr: Error Interrupt. This interrupt is generated when an ERROR response is received from an AHB slave on the HRESP bus during a DMA transfer. In addition, the DMA transfer is cancelled, and the channel is disabled.

The DMA_RAW_x, DMA_STAT_x, DMA_MASK_x, and DMA_CLR_x registers are provided to manage interrupts. The DMA_MASK_x registers is used to enable or disable the block transfer complete interrupt, DMA transfer complete interrupt, and error interrupt. By reading the DMA_STAT_x registers or DMA_RAW_x registers, you can check whether the interruption have occurred. To clear interrupts, write 1 to the DMA_CLR_x registers.

• DMA_MASK_x registers: Used to enable or disable the block transfer complete interrupt, DMA transfer complete interrupt, and error interrupt.
• DMA_STAT_x or DMA_RAW_x registers: Used to reply whether the interruption have occurred.
• DMA_CLR_x registers: Write 1 to DMA_CLR_x to clear interrupts.

Each channel of DMA can communicate with designated peripheral devices through the assigned hardware handshaking interface. The hardware handshaking interfaces are assigned as shown in the following table. The developer can program the CFG_HIx.DEST_PER or CFG_HIx.SRC_PER to assign a handshaking interface for each channel source and destination.

表 516 Hardware handshaking interfaces

DMA0 Request	Peripheral Name	Peripheral Description
0x0	BLE CTE	BLE Constant Tone Extension
0x1	PWM	PWM Coding
0x2	SPIM TX	SPI Master Transmit
0x3	SPIM RX	SPI Master Receive
0x4	SPIS TX	SPI Slave Transmit
0x5	SPIS RX	SPI Slave Receive
0x6	UART0 TX	UART0 Transmit
0x7	UART0 RX	UART0 Receive
0x8	UART1 TX	UART1 Transmit
0x9	UART1 RX	UART1 Receive
0xA	SNSADC	Sense ADC
0xB	NC	/
0xC	I2C0 TX	I2C0 Transmit
0xD	I2C0 RX	I2C0 Receive
0xE	I2C1 TX	I2C1 Transmit
0xF	I2C1 RX	I2C1 Receive