Real-Time Counter (RTC/Calendar)

The Real-time Counter (RTC) modules provide a generic, low-power timer running on a low-frequency clock source. Because the RTC modules are in the AON domain, the timer can keep running when the MCU is off. The modules can also wake up the system from sleep mode.

The RTC tick event interrupt module enables low-power "tick-less" RTOS implementation as it optionally provides a regular interrupt source for an RTOS without the need to use the ARM® SysTick feature. Using the RTC tick event rather than the SysTick allows the CPU to be powered down while still keeping RTOS scheduling active.

Main Features

One ordinary compare interrupt
One tick event, supporting one-time counting and auto loading mode
32-bit up-counter register, supporting reading and writing
32-bit compare register, supporting reading and writing
32-bit down-tick register, supporting reading and writing
One clock divider, supporting NO_DIV, DIV_2, DIV_4, DIV_8, DIV_16, DIV_32, DIV_64, and DIV_128
Flexible clock source selections from LFRC_32K or LFXO_32K
An independent interrupt entry

Functional Description

The software has to enable RTC PMU LPD (GFG0.EN = 1) before using the RTC.
The CFG1 register is a read/write register when the RTC is disabled, and it is read only when the RTC is enabled. Writing to the CFG1 register when the RTC is enabled has no effect.
The OVERFLOW, ALARM, and tick event interrupts are enabled by default.
When RTC is enabled, the TIMER_R register starts to count. When users set the values of the TIMER_W register and the VAL bit to 1, the calendar module synchronizes the count value to the TIMER_R register and starts timing.
When RTC is disabled, all register values must be cleared to restore the default values.
When the value of the TIMER_R register is equal to that of the ALARM_R register, the ordinary compare interrupt is triggered.
RTC tick event interrupt register is a value-decreasing register. When the auto reloading mode is set (CFG0.TICK_MDOE = 1), the value of the counter (TICK_W) is automatically reloaded (TICK_R) when the interrupt is triggered.
When the count value of the TIMER_R register overflows, the overflow interrupt is triggered, and the TIMER_R register continues counting from 0.

Note:

The AON_WDT, RTC, and SLP TIMER share the same clock source selection. The clock source can be LFRC_32K or LFXO_32K which are described in "Clocks".

Registers

CFG0

Name: CFG0 Register
Description: This register sets RTC configurations.
Base Address: 0x4000A600
Offset: 0x00
Reset Value: 0x00000000

表 365 CFG0
Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24	CFG	W	0x0	Writing 1 to this register triggers the calendar timer configuration.
23:11	RSVD	R		Reserved bits
10	TICK_MDOE	RW	0x0	Set the RTC tick event mode. 0: One-time 1: Auto reloading
9	TICK_SET	RW	0x0	Set the RTC tick event timer value.
8	TICK_EN	RW	0x0	Enable RTC tick event.
7:5	RSVD	R		Reserved bits
4	WRAP_CLR	RW	0x0	Clear the wrap counter.
3	ALARM_SET	RW	0x0	Set the RTC ALARM timer value.
2	ALARM_EN	RW	0x0	Enable RTC ALARM timer.
1	TIME_SET	RW	0x0	Set the RTC initial timer value.
0	EN	RW	0x0	Enable RTC timer.

CFG1

Name: CFG1 Register
Description: This register is used to set the frequency division coefficient.
Base Address: 0x4000A600
Offset: 0x4
Reset Value: 0x00000000

表 366 CFG1
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R		Reserved bits
2:0	DIV	RW	0x0	0x0: NO_DIV. No division; counting at SLP_CLK 0x1: DIV_2. Counting at 1/2 of SLP_CLK 0x2: DIV_4. Counting at 1/4 of SLP_CLK 0x3: DIV_8. Counting at 1/8 of SLP_CLK 0x4: DIV_16. Counting at 1/16 of SLP_CLK 0x5: DIV_32. Counting at 1/32 of SLP_CLK 0x6: DIV_64. Counting at 1/64 of SLP_CLK 0x7: DIV_128. Counting at 1/128 of SLP_CLK

INT_EN

Name: INT_EN Register
Description: This register is used to enable RTC interrupts.
Base Address: 0x4000A600
Offset: 0x14
Reset Value: 0x00000007

表 367 INT_EN
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R		Reserved bits
2	TICK	RW	0x1	RTC tick event interrupt. Write 1 to enable the interrupt.
1	WRAP	RW	0x1	RTC overflow interrupt. Write 1 to enable the interrupt.
0	ALARM	RW	0x1	RTC COMPARE interrupt. Write 1 to enable the interrupt.

INT_STAT

Name: IRQ_STAT Register
Description: This register is used to get interrupt status of the RTC.
Base Address: 0x4000A600
Offset: 0x18
Reset Value: 0x00000000

表 368 IRQ_STAT
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R		Reserved bits
2	TICK	RW	0x0	RTC tick event interrupt. Write 1 to clear the interrupt.
1	WRAP	RW	0x0	RTC overflow interrupt. Write 1 to clear the interrupt.
0	ALARM	RW	0x0	RTC COMPARE interrupt. Write 1 to clear the interrupt.

STAT

Name: STAT Register
Description: This register is used to get the RTC status.
Base Address: 0x4000A600
Offset: 0x38
Reset Value: 0x00000000

表 369 STAT
Bits	Field Name	RW	Reset	Description
31:12	RSVD	R		Reserved bits
11:8	WRAP_CNT	R	0x0	Calendar timer wrap counter
7:5	RSVD	R		Reserved bits
4	BUSY	R	0x0	Calendar timer is busy. The application layer can perform other operations until this bit is set is 0.
3:1	RSVD	R		Reserved bits
0	STAT	R	0x0	RTC timer is running.

ALARM_W

Name: ALARM_W Register
Description: This register is used to set the ALARM timer value.
Base Address: 0x4000A600
Offset: 0x40
Reset Value: 0x00000000

表 370 ALARM_W
Bits	Field Name	RW	Reset	Description
31:0	VAL	RW	0x0	W: RTC ALARM timer value to configure R: The set value. Read ALARM_R to get the current internal value.

TIMER_W

Name: TIMER_W Register
Description: This register is used to set the RTC timer value.
Base Address: 0x4000A600
Offset: 0x44
Reset Value: 0x00000000

表 371 TIMER_W
Bits	Field Name	RW	Reset	Description
31:0	VAL	RW	0x0	W: RTC timer value to configure R: The set value. Read TIMER_R to get the current internal value.

TICK_W

Name: TICK_W Register
Description: This register is used to set the tick event timer value.
Base Address: 0x4000A600
Offset: 0x48
Reset Value: 0x00000000

表 372 TICK_W
Bits	Field Name	RW	Reset	Description
31:0	VAL	RW	0x0	W: RTC tick event timer value to configure R: The set value. Read TICK_R to get the current internal value.

TIMER_R

Name: TIMER_R Register
Description: This register is used to get the internal value of the RTC timer.
Base Address: 0x4000A600
Offset: 0x50
Reset Value: 0x00000000

表 373 TIMER_R
Bits	Field Name	RW	Reset	Description
31:0	VAL	R	0x0	Current internal value of the RTC timer

ALARM_R

Name: ALARM Register
Description: This register is used to get the value of the RTC ALARM timer.
Base Address: 0x4000A600
Offset: 0x54
Reset Value: 0x00000000

表 374 ALARM
Bits	Field Name	RW	Reset	Description
31:0	VAL	R	0x0	Current internal value of the RTC ALARM timer

TICK_R

Name: TICK_RD Register
Description: This register is used to get the value of the RTC tick event timer.
Base Address: 0x4000A600
Offset: 0x58
Reset Value: 0x00000000

表 375 TICK_RD
Bits	Field Name	RW	Reset	Description
31:0	VAL	R	0x0	Current internal value of the RTC tick event timer.