Timer

Introduction

The device has two instances of Timer module. Each Timer module features a 32-bit down counter and 4-channel I/O capture registers. Because the Timer is in the MCU subsystem domain, Timer interrupt is not available during sleep, and the running Timer will not prevent MCU from sleeping. In active mode, when the Timer is restarted after being stopped, it will continue to count down from the stop time.

Main Features

Generate an interrupt when the 32-bit down counter reaches 0.
The 4-channel I/O capture function contains rising edge capture, falling edge capture, and both edge capture.
The clock source of the Timer follows the system clock.
Each Timer module has an independent interrupt entry.
Timer pauses when the MCU is suspended.

Functional Description

Counter

The Timer can generate a COUNTDONE interrupt request signal when the 32-bit down counter reaches 0. The COUNTDONE interrupt request is held until it is cleared by writing 1 to the COUNTDONE_INT_STAT bit in the INTSTAT register.
If the Timer count reaches 0 and, at the same time, the software clears the previous COUNTDONE interrupt status, the COUNTDONE_INT_STAT bit is set to 1.
When the value of the RELOAD register is configured to 0, no COUNTDONE interrupt are generated.
The RELOAD value only represents the count-down number of timers. If you want to configure a specific duration (for example, µs, ms, or s), you need to use the following formula:
When the CTRL.EN bit is set to 1, the timer is running. Changing the value in the RELOAD register will take effect immediately, and the timer will count down from the new RELOAD value.

I/O Capture

I/O should be set to input mode for Timer I/O capture function.
I/O capture function supports falling edge capture, rising edge capture and both edge capture which can be configured the CHx_EDGE_DET bit in the CTRL register.
Each Timer module can capture GPIO_0 to GPIO_13, AON_GPIO_0 to AON_GPIO_7, and MSIO_0 to MSIO_9. The CHx interrupt request is held until it is cleared by writing 1 to the CHx_INT_STAT bit in the INTSTAT register.
The captured value of each channel will be put into the corresponding CHANNELx_VAL register. When multiple values are captured continuously by the same channel, only the last value is retained in CHANNELx_VAL register.

Registers

CTRL

Name: Timer Control Register
Description: The CTRL register configures capture channel parameters and enables the software to control the Timer.
Base Address: 0x40000000 + x*0x1000
Offset: 0x00
Reset Value: 0x00

Note:

*x is used to identify the Timer Module. The “x” can be 0 or 1.

表 299 CTRL
Bits	Field Name	RW	Reset	Description
31:29	RSVD	R		Reserved bits
28:24	CH3_PIN_SELECT	RW	0x0	GPIO PIN select of channel3. Value: 0x0–0xC: GPIO_0 to GPIO_13 0xD–0x14: AON_GPIO_0 to AON_GPIO_ 7 0x15–0x1E: MSIO_0 to MSIO_9
23:19	CH2_PIN_SELECT	RW	0x0	GPIO PIN select of channel2. Value: 0x0–0xC: GPIO_0 to GPIO_13 0xD–0x14: AON_GPIO_0 to AON_GPIO_ 7 0x15–0x1E: MSIO_0 to MSIO_9
18:14	CH1_PIN_SELECT	RW	0x0	GPIO PIN select of channel1. Value: 0x0–0xC: GPIO_0 to GPIO_13 0xD–0x14: AON_GPIO_0 to AON_GPIO_ 7 0x15–0x1E: MSIO_0 to MSIO_9
13:9	CH0_PIN_SELECT	RW	0x0	GPIO PIN select of channel0. Value: 0x0–0xC: GPIO_0 to GPIO_13 0xD–0x14: AON_GPIO_0 to AON_GPIO_ 7 0x15–0x1E: MSIO_0 to MSIO_9
8:7	CH3_EDGE_DET	RW	0x0	Capture type of channel3. Value: 0x0: None 0x1: Falling edge capture 0x2: Rising edge capture 0x3: Both edge capture
6:5	CH2_EDGE_DET	RW	0x0	Capture type of channel2. Value: 0x0: None 0x1: Falling edge capture 0x2: Rising edge capture 0x3: Both edge capture
4:3	CH1_EDGE_DET	RW	0x0	Capture type of channel1. Value: 0x0: None 0x1: Falling edge capture 0x2: Rising edge capture 0x3: Both edge capture
2:1	CH0_EDGE_DET	RW	0x0	Capture type of channel0. Value: 0x0: None 0x1: Falling edge capture 0x2: Rising edge capture 0x3: Both edge capture
0	EN	RW	0x0	Timer enable bit Value: 0x0: Disable the Timer. 0x1: Enable the Timer.

VALUE

Name: Timer Value Register
Description: The VALUE register indicates the current value of the decrementing counter.
Base Address: 0x40000000 + x*0x1000
Offset: 0x04
Reset Value: 0x00

表 300 VALUE
Bits	Field Name	RW	Reset	Description
31:0	VALUE	R	0x0	Current value

RELOAD

Name: Timer Reload Register
Description: When this register is written to, the count value takes effect immediately from a new RELAOD value.
Base Address: 0x40000000 + x*0x1000
Offset: 0x08
Reset Value: 0x00

表 301 RELOAD
Bits	Field Name	RW	Reset	Description
31:0	RELOAD	RW	0x0	Sets reload value.

INTEN

Name: Timer Interrupt Enable Register
Description: The INTEN register indicates interrupt enable configuration of COUNTDONE, CHANNEL0 capture, CHANNEL1 capture, CHANNEL2 capture, or CHANNEL3 capture.
Base Address: 0x40000000 + x*0x1000
Offset: 0x0C
Reset Value: 0x00000000

表 302 INTEN
Bits	Field Name	RW	Reset	Description
31:5	RSVD	R		Reserved bits
4	CH3_INT_EN	RW	0x0	Channel 3 I/O capture interrupt enable bit
3	CH2_INT_EN	RW	0x0	Channel 2 I/O capture interrupt enable bit
2	CH1_INT_EN	RW	0x0	Channel 1 I/O capture interrupt enable bit
1	CH0_INT_EN	RW	0x0	Channel 0 I/O capture interrupt enable bit
0	COUNTDONE_INT_EN	RW	0x0	Count done interrupt enable bit

INTSTAT

Name: Timer Interrupt Status Register
Description: The INTSTAT register indicates the interrupt status from the counter. Writing one to each bit of INTSTAT register clears the corresponding interrupt.
Base Address: 0x40000000 + x*0x1000
Offset: 0x10
Reset Value: 0x00000000

表 303 INTSTAT
Bits	Field Name	RW	Reset	Description
31:5	RSVD	R		Reserved bits
4	CH3_INT_STAT	WC	0x0	Channel 3 captured; write 1 to clear.
3	CH2_INT_STAT	WC	0x0	Channel 2 captured; write 1 to clear.
2	CH1_INT_STAT	WC	0x0	Channel 1 captured; write 1 to clear.
1	CH0_INT_STAT	WC	0x0	Channel 0 captured; write 1 to clear.
0	COUNTDONE_INT_STAT	WC	0x0	Count done; write 1 to clear.

CHANNEL0_VAL

Name: CHANNEL0 Capture Value
Description: The CHANNEL0_VAL register indicates the edge capture value.
Base Address: 0x40000000 + x*0x1000
Offset: 0x14
Reset Value: 0x00000000

表 304 CHANNEL1_VAL
Bits	Field Name	RW	Reset	Description
31:0	CH0_VAL	R	0x0	When the desired I/O edge is captured, the value of the current counter is stored.

CHANNEL1_VAL

Name: CHANNEL1 Capture Value
Description: The CHANNEL1_VAL register indicates the edge capture value.
Base Address: 0x40000000 + x*0x1000
Offset: 0x18
Reset Value: 0x00000000

表 305 CHANNEL0_VAL
Bits	Field Name	RW	Reset	Description
31:0	CH1_VAL	R	0x0	When the desired I/O edge is captured, the value of the current counter is stored.

CHANNEL2_VAL

Name: CHANNEL2 Capture Value
Description: The CHANNEL2_VAL register indicates the edge capture value.
Base Address: 0x40000000 + x*0x1000
Offset: 0x1C
Reset Value: 0x00000000

表 306 CHANNEL2_VAL
Bits	Field Name	RW	Reset	Description
31:0	CH2_VAL	R	0x0	When the desired I/O edge is captured, the value of the current counter is stored.

CHANNEL3_VAL

Name: CHANNEL3 Capture Value
Description: The CHANNEL3_VAL register indicates the edge capture value.
Base Address: 0x40000000 + x*0x1000
Offset: 0x20
Reset Value: 0x00000000

表 307 CHANNEL3_VAL
Bits	Field Name	RW	Reset	Description
31:0	CH3_VAL	R	0x0	When the desired I/O edge is captured, the value of the current counter is stored.