Block Diagram
图 90 shows the following functional groupings of the main interfaces to the DMA controller block:
- DMA hardware request interface
- Five channels
- 32 bytes FIFO for Channel 0 and 16 bytes FIFO per other channel for source and destination
- Arbiter
- AHB master interface
- AHB slave interface
图 91 illustrates a peripheral-to-peripheral DMA transfer, where peripheral A (source) uses a hardware handshaking interface, and peripheral B (destination) uses a software handshaking interface. For example, the request to send data to peripheral B is originated by the CPU, while writing to peripheral B is handled by the DMA controller. The channel source and destination arbitrate independently for the AHB master interface, along with other channels.
