Functional Overview

The Power Management Unit (PMU), consisting of a DC-DC converter and a number of LDOs, is responsible for generating all required voltages for different blocks in the device.

In active mode, both the DC-DC converter and SYS_LDO can generate voltage VDDRF/VDDVCO to power the RF domain. If the DC-DC converter is selected, lower power consumption can be obtained. In other words, the SYS_LDO has better power supply rejection ratio (PSRR) and can improve RF performance. To transmit at +15 dBm, SYS_LDO supply mode is recommended. The CORE_LDO regulator generates the voltage DIGCORE for the digital logic blocks and can also power the memory and eFuse.

An AON_LDO regulator is used to supply its AON modules that stays ON when both the MCU subsystem and the Bluetooth LE subsystem are OFF. The RET_LDO regulator generates a lower voltage VRET for content retention to the memories where their content is needed after wakeup. Both ANA_IO_LDO and STB_IO_LDO supply power to the I/O domain, and also generate voltage VDD_EFLASH to supply power to Flash. ANA_IO_LDO provides I/O voltage to supply the I/O domain in active mode, and STB_IO_LDO is still working in sleep mode.

As shown in the figure above, the power supply architecture is based on the PMU that generates the following supplies from an external supply VBATL.

• DC-DC/SYS_LDO: supply for RF domain and CORE_LDO (enabled by default).
• CORE_LDO: supply for digital logic blocks (enabled by default).
• AON_LDO: supply for AON blocks (enabled by default).
• RET_LDO: retention supply for memory instances (enabled by default).
• ANA_IO_LDO: Used to generate the I/O voltage to supply the pads of device and the external devices connecting to the SoC. ANA_IO_LDO is also used to supply power to the stacked Flash (enabled by default).
• STB_IO_LDO: Used to replace ANA_IO_LDO during sleep, which can help reduce sleep current.
• VDDIO1: supply for I/O1 group; from external power voltage or VIO_LDO_OUT.

Both VBATL and VBAT_RF come from the battery voltage VBAT. The VBAT_RF voltage is supplied to the RF domain only, and the VBATL voltage is the input voltage of all blocks.

As shown in the figure below, the startup sequence of each power module and clock in the SoC follows certain rules.

1. As the voltage of the VBAT gradually increases, when the corresponding voltage value is reached, AON_LDO and RET_LDO will be powered on first.
2. The Brown Out Reset (BOR) signal will be released after reaching the specified voltage. There is about 10 µs delay to generate a deglitch after releasing the BOR. Ensure that the AON_LDO and RET_LDO startup is complete.
3. The low frequency clock sources LFRC_32K and RNG_OSC start working after AON_LDO and RET_LDO startup.
4. Subsequently, the DC-DC converter and SYS_LDO begin to start.
5. After waiting for the DC-DC converter and SYS_LDO to stabilize for a period of time, CORE_LDO and ANA_IO_LDO will start to provide power to the digital domain and I/Os. At the same time, the high frequency clock sources HFXO_32M, HFRC_192M and CPLL_192M start working. Since the crystal oscillator needs a certain amount of time to stabilize, the actual generation of the HFXO_32M clock will be slower than the HFRC_192M clock. Similarly, the CPLL_192M needs the HFXO_32M to get stable before it can work normally.
6. When both the basic power modules and the basic clock sources are working, the Power-on Reset (POR) signal is released, and the digital domain starts to work as well. Simultaneously, the ANA_IO_LDO output generates a voltage drop of 100 mV, indicating that the internal POR signal has been released. After completing a series of initialization of digital states, the CPU starts to work, allowing software to start running.