Interrupt
In addition to supporting 16 system exceptions within the Arm®Cortex®-M4F, the device also supports 35 external interrupts with 256 programmable priority levels. In some cases, a single peripheral can generate multiple different interrupts (such as BOD/Bluetooth LE interrupt). Most interrupts are connected directly to the NVIC, but all wakeup sources on the always-on domain are connected to the Power State Controller (PSC) outside of the Arm®Cortex®-M4F, allowing the interrupt sources to wake up the Arm®Cortex®-M4F core from the sleep mode. In most cases, developers do not need to change the interrupt source.
The Cortex®-M4F allows developers to assign various interrupts to different priority levels based on the application requirements. To maintain the stability of Bluetooth connection, it is recommended that the priority of Bluetooth interrupt should be set to the highest. In most cases, developers do not need to change priority levels, and the SoC has been configured with default priorities to meet most application requirements.
One additional feature of the Cortex®-M4F interrupt architecture is the ability to relocate the vector table to different addresses. The software can move the vector table into SRAM and reassign the interrupt service routine entry addresses on demand, but it should be noted that the remapping start address of the interrupt vector table should be aligned with 0x200. For example, the vector table base address should be set as 0x00000000, 0x00000200, or 0x00000400.
All non-programmable and programmable interrupts including those that can wake up the MCU from sleep mode are shown in 表 9 and 表 10. The width of interrupt priority control register is 8 bits, in which bit 7–bit 4 are used for preemption priority and bit 3–bit 0 are used for subpriority. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority.
| No. | Name | Default Priority | Wake up MCU | Description |
|---|---|---|---|---|
1 |
Reset_IRQ |
-3 |
Reset exception |
|
2 |
NMI_IRQn |
-2 |
Non-maskable interrupt |
|
3 |
HardFault_IRQ |
-1 |
All classes of fault. This interrupt occurs when the corresponding fault handler cannot be activated because it is disabled or masked by exception masking. |
| No. | Name | Default Preemption Priority | Default Subpriority | Wake up MCU | Description |
|---|---|---|---|---|---|
|
4 |
MemManage_IRQ |
- |
- |
Memory management fault; caused by MPU violation or invalid accesses |
|
|
5 |
BusFault_IRQ |
- |
- |
Error response received from the bus system |
|
|
6 |
UsageFault_IRQ |
- |
- |
Usage fault; typical causes are invalid instructions or invalid state transition attempts. |
|
|
7–10 |
Reserved |
- |
- |
Unused |
|
|
11 |
SVCall_IRQ |
0 |
0 |
Supervisor call via SVC instruction |
|
|
12 |
DebugMonitor_IRQ |
- |
- |
Debug monitor – for software-based debugging |
|
|
13 |
Reserved |
- |
- |
Unused |
|
|
14 |
PendSV_IRQ |
15 |
15 |
Pendable request for system service |
|
|
15 |
SysTick_IRQ |
15 |
15 |
System tick timer interrupt |
|
|
16 |
WDT_IRQ |
8 |
0 |
System watchdog timer interrupt |
|
|
17 |
BLE_SDK_IRQ |
15 |
15 |
Bluetooth LE software development kit (SDK) schedule interrupt |
|
|
18 |
BLE_IRQ |
2 |
0 |
√ |
Bluetooth LE interrupt |
|
19 |
DMA0_IRQ |
6 |
0 |
DMA0 interrupt |
|
|
20 |
SPI_M_IRQ |
8 |
0 |
SPI master interrupt |
|
|
21 |
SPI_S_IRQ |
8 |
0 |
SPI slave interrupt |
|
|
22 |
EXT0_IRQ |
8 |
0 |
GPIO_0 interrupt |
|
|
23 |
EXT1_IRQ |
8 |
0 |
GPIO_1 interrupt |
|
|
24 |
TIMER0_IRQ |
12 |
0 |
TIMER0 interrupt |
|
|
25 |
TIMER1_IRQ |
12 |
0 |
TIMER1 interrupt |
|
|
26 |
DUAL_TIMER_IRQ |
12 |
0 |
DUAL_TIMER interrupt |
|
|
27 |
DDVS_ERR_IRQ |
8 |
0 |
DDVS error interrupt |
|
|
28 |
UART0_IRQ |
10 |
0 |
UART0 interrupt |
|
|
29 |
UART1_IRQ |
10 |
0 |
UART1 interrupt |
|
|
30 |
I2C0_IRQ |
8 |
0 |
I2C0 interrupt |
|
|
31 |
I2C1_IRQ |
8 |
0 |
I2C1 interrupt |
|
|
32 |
RNG_IRQ |
8 |
0 |
TRNG interrupt |
|
|
33 |
BOD_ASSERT_IRQ |
8 |
0 |
Brown-out detection interrupt |
|
|
34 |
XQSPI_IRQ |
8 |
0 |
XQSPI interrupt |
|
|
35 |
BLESLP_IRQ |
2 |
0 |
√ |
Bluetooth LE timer done interrupt |
|
36 |
SLPTIMER_IRQ |
12 |
0 |
√ |
Sleep timer done interrupt |
|
37 |
AON_EXT_IRQ |
8 |
0 |
√ |
AON GPIO interrupt |
|
38 |
AON_WDT_IRQ |
8 |
0 |
√ |
AON watchdog timer interrupt |
|
39 |
RTC1_IRQ |
8 |
0 |
√ |
Real-Timer counter interrupt |
|
40 |
COMM_CORE_IRQ |
8 |
0 |
AHB/APB timeout interrupt |
|
|
41 |
SLP_FAIL_IRQ |
8 |
0 |
Sleep failure interrupt |
|
|
42 |
CTE_FULL_IRQ |
8 |
0 |
CTE full interrupt |
|
|
43 |
BOD_DEASSERT_IRQ |
8 |
0 |
Brown out detection deassert interrupt |
|
|
44 |
COMP_IRQ |
8 |
0 |
√ |
Comparator interrupt |
|
45 |
CPLL_DRIFT_IRQ |
8 |
0 |
CPLL drift interrupt |
|
|
46 |
CLK_CALIB_IRQ |
8 |
0 |
Clock calibration_0/1 interrupt |
|
|
47 |
BLE_PWR_ON_IRQ |
2 |
0 |
Bluetooth LE sequencer power on done interrupt |
|
|
48 |
BLE_PWR_DN_IRQ |
8 |
0 |
Bluetooth LE sequencer power off done interrupt |
|
|
49 |
PLL_STATE_IRQ |
8 |
0 |
PLL state interrupt |
|
|
50 |
PWM0_DONE_IRQ |
8 |
0 |
PWM0 coding mode done interrupt |
