Functional Overview
Clock system is an important structure in the SoC. The clock sources can be derived from a series of internal or external high and low frequency oscillators. Different modules can use corresponding clock source according to their own requirements.
The device has both high-frequency clock sources and low-frequency clock sources, as detailed below.
High-frequency clock sources:
- HFXO_32M (Enabled by default)
- CPLL_192M (Enabled by default)
- HFRC_192M (Enabled by default)
Low-frequency clock sources:
- RNG_OSC (Enabled by default)
- LFXO_32K
- LFRC_32K (Enabled by default)
The figure below shows the basic clock structure of the device. The power control and startup sequence of the clocks follow the description in "PMU".
Usually, there are two options for the high-frequency clock source of the MCU. The CPLL_192M clock generated by the phase-locked loop frequency multiplication through the 32 MHz external crystal oscillator and the HFRC_192M clock can be used for the high-frequency clock source. During the MCU working stage, either CPLL_192M or HFRC_192M must be enabled. Due to the high accuracy requirements of RF for the clock, the external crystal should meet the offset requirements of the Bluetooth LE specifications.
The system clock and system serial clock can be configured independently. In the SDK, the default value of the system serial clock is 64 MHz.
The AON Power State Controller clock (pwr_ctrl_clk) comes from a 256 kHz ring oscillator (RNG_OSC) with a choice of 32 kHz clock. The clocks for the various slow AON timer modules can be generated from a choice of three sources: 32 kHz ring oscillator (RNG_OSC), low-frequency RC oscillator (LFRC_32K), and low-frequency crystal (LFXO_32K) based on 32 kHz crystal.
For XO clock sources such as HFXO_32M and LFXO_32K, the device does not require external capacitors except the crystal itself. It is recommended to choose a crystal with low load capacitance (6 pF–8 pF). Low load capacitance will reduce startup time and current consumption. For specified parameters and recommended selection of external crystals, refer to GR533x Hardware Design Guidelines.
To reduce power consumption, an integer clock supporting Phase-Locked Loop (CPLL_192M) is used to generate the main system clock for both RF and digital sections. Frequency dividers are used to provide slower frequencies for different blocks of the device. CPLL_192M is also used to tune the desired frequency hopping for each packet. The settling time of the CPLL_192M is designed to be within the time defined by the Bluetooth LE specifications to maintain the interframe space (IFS) timing.
| Clock Source | Active Mode/IDLE Mode | Sleep Mode |
|---|---|---|
| HFXO_32M | ON (Conditionally OFF) | Conditionally OFF |
| CPLL_192M | ON (Conditionally OFF) | Normally OFF |
| HFRC_192M | ON (Conditionally OFF) | Normally OFF |
| RNG_OSC | ON | ON |
| LFXO_32K | ON (Conditionally OFF) | ON (Conditionally OFF) |
| LFRC_32K | ON (Conditionally OFF) | ON (Conditionally OFF) |
The usage of each clock source in different power modes is described in the table above. Developers can selectively turn off some clock sources to reduce the average power consumption of the system. Some clock sources are turned off conditionally, which can be found in the description of each clock in the sections below. Note that when a clock is turned on, it usually takes time for the crystal to start oscillating, as well as the output to fully stabilize. To prevent erroneous clocks, the SDK implements automatic calculation of the time required for different clocks to stabilize and delays until the clocks are stabilized before being fully activated.
