Sleep Timer (SLP TIMER)

Introduction

The Sleep Timer is a 32-bit hardware timer that can wake the SoC up from sleep state. It can also be used when the SoC is awake.

32-bit down counter running with two different clock sources: LFXO_32K clock (32.768 kHz) and LFRC_32K clock (about 32 KHz).
Three operation modes: Basic Sleep Timer, Single-load Sleep Timer, and Auto-reload Sleep Timer

The Sleep Timer supports three operation modes:

Mode 0 – Basic Sleep Timer: This is the original mode of the Sleep Timer. It only counts down when the SoC is in sleep state and is not activated when the SoC is awake.
Mode 1 – Single-load Sleep Timer: In this mode, the timer starts counting as soon as it is put in this mode and it continues to count down even when the SoC is awake. The timer stops when the counter hits zero. The time-out signal is saved as a timeout event.
Mode 2 – Auto-reload Sleep Timer: Similar to Single-load Sleep Timer mode, the timer does not stop counting down even when the SoC is awake. However, the timer can automatically reload to a value that is the same as that before automatic reload until it is disabled by the MCU.

Note:

The AON_WDT, RTC, and SLP TIMER share the same clock source selection. The clock source can be LFRC_32K or LFXO_32K which are described in “Clocks”.

表 376 CFG_0
Bits	Field Name	RW	Reset	Description
31:25	RSVD	R		Reserved bits
24	CFG	W	0x0	Write: Writing 1 to this register triggers the Sleep Timer configuration. Writing to this bit during sleep timer configuration will generate a configuration failure interrupt. Read: The read value is always 0.
23:4	RSVD	R		Reserved bits
3	COUNT_MODE	RW	0x0	Value: 0x1: Count during sleep only. 0x0: Count in any condition.
2	MODE	RW	0x0	Value: 0x1: Single-load mode 0x0: Auto-reload mode
1	VAL_SET	RW	0x0	Set the timer value; write 1 to make the timer value effective.
0	EN	RW	0x0	Enable Sleep Timer. Value: 0x1: Enable Sleep Timer. 0x0: Disable Sleep Timer.

表 377 STS
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R		Reserved bits
1	BUSY	R	0x0	Sleep Timer is running.
0	STAT	R	0x0	Sleep Timer is busy. Do not configure this bit if the signal is 1.

表 378 TIMER_W
Bits	Field Name	RW	Reset	Description
31:0	VAL_SET	RW	0x0	Write: Write the Sleep Timer value to the VAL_W register. Read: The set value. Read SLP_TIMER_VAL_RD in the VAL_R register for the current interval value.

表 379 TIMER_R
Bits	Field Name	RW	Reset	Description
31:0	VAL_READ	R	0x0	Read internal value of the Sleep Timer.