Always-on Watchdog (AON_WDT)

Introduction

The Always-on Watchdog (AON_WDT) is a 32-bit countdown hardware timer. When the AON_WDT counter counts to 0, a system reset signal is sent, and when the counter value decreases to the set warning value, an interrupt signal is generated. Because the AON_WDT timer is in the AON domain, it can keep running when the MCU is off.

Main Features

The MCU_CLK_CTRL register is a read/write register which controls clock source selections.
32-bit down counter running with a low-power clock
Generate an interrupt to warn the MCU when the 32-bit down counter reaches the alarm values
16-bit alarm register, supporting reading and writing
Flexible clock source selections from LFRC_32K or LFXO_32K
An independent interrupt entry
Support write access protection

Functional Description

The LOCK register enables or disables write accesses to all other registers. This is to prevent malicious software from disabling the watchdog functionality. Writing a value of 0x15CC5A51 (LOCK.LOCK_SET[31:1]) enables write accesses to all other registers. Writing any other value to the LOCK register disables the write accesses.
When the AON_WDT is disabled, all register values must be cleared to restore the default values.
When the CFG0.EN bit is set to 1, the value of the TIMER_W register is automatically loaded into the TIMER_R register, and the value starts to decrease.
The AON_WDT alarm interrupt is triggered when the value of the TIMER_R register decrements to the value of the ALARM_R register.
When the TIMER_R count value decrements to 0, the system restarts.

Registers

MCU_CLK_CTRL

Name: MCU_CLK_CTRL Register
Description: This register sets AON_WDT CLK configurations.
Base Address: 0x4000A000
Offset: 0x0
Reset Value: 0x42040202

表 357 MCU_CLK_CTRL
Bits	Field Name	RW	Reset	Description
5:4	WDT_CLK_SEL	WO	0x0	0x02: LFRC_32K (LFRC 32 kHz clock) 0x03: LFXO_32K (LF_XO 32 kHz clock)
3:0	RSVD	RO	0x0	Reserved bits

CFG_0

Name: CFG_0 Register
Description: This register sets AON_WDT configurations.
Base Address: 0x4000A700
Offset: 0x0
Reset Value: 0x00000000

表 358 CFG_0
Bits	Field Name	RW	Reset	Description
31:25	RSVD	R	0x0	Reserved bits
24	CFG	WO	0x0	Writing 1 to this bit triggers the watchdog timer configuration.
23:5	RSVD	R	0x0	Reserved bits
4	ESD_PROTECT	WR	0x0	0x0: The backup counter do not take effect. 0x1: When there is difference between the working counter and the backup counter, a watchdog reset will be generated.
3	ALARM_SET	RW	0x0	Set the timer alarm value.
2	ALARM_EN	RW	0x0	Enable AON WDT alarm.
1	TIMER_SET	WO	0x0	Enable AON WDT timer reload (feed).
0	EN	RW	0x0	Enable AON WDT.

LOCK

Name: LOCK Register
Description: This register can prevent other registers of AON_WDT from being overwritten.
Base Address: 0x4000A700
Offset: 0x4
Reset Value: 0x00000000

表 359 LOCK
Bits	Field Name	RW	Reset	Description
31:1	LOCK_SET	WO	–	Enable write access to all other registers by writing 0x15CC5A51. Disable write accesses by writing any other value to the LOCK register.
0	STAT	RO	0	0x0: Unlocked. Writing to other watchdog registers is enabled. 0x1: Locked. Writing to other watchdog registers is disabled.

STAT

Name: STAT Register
Description: This register can be used to get status of AON_WDT.
Base Address: 0x4000A700
Offset: 0x38
Reset Value: 0x00000000

表 360 STAT
Bits	Field Name	RW	Reset	Description
31:2	RSVD	R	0x0	Reserved bits
1	BUSY	R	0x0	Watchdog timer is busy. The application layer can perform other operations until this bit is set to 0.
0	STAT	R	0x0	AON WDT is running.

TIMER_W

Name: TIMER_W Register
Description: This register is used to configure the initial AON_WDT value.
Base Address: 0x4000A700
Offset: 0x40
Reset Value: 0x00000000

表 361 TIMER_W
Bits	Field Name	RW	Reset	Description
31:0	VAL	RW	0x0	Write: Write the initial AON WDT value to the register. Read: Read the initial AON WDT value that users have configured. Read TIMER_R to get the current internal value.

ALARM_W

Name: ALARM_W Register
Description: This register is used to configure the AON_WDT alarm value.
Base Address: 0x4000A700
Offset: 0x44
Reset Value: 0x64

表 362 ALARM_W
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R	0x0	Reserved bits
15:0	VAL	RW	0x64	Write: Write an AON WDT alarm value to the register. Read: Read the AON WDT alarm value that users have configured. Read ALARM_R to get the current internal alarm value of AON WDT.

TIMER_R

Name: TIMER_R Register
Description: This register is used to get the current value of AON_WDT.
Base Address: 0x4000A700
Offset: 0x4C
Reset Value: 0x00000000

表 363 TIMER_R
Bits	Field Name	RW	Reset	Description
31:0	VAL	RO	0x0	Current internal value of AON WDT

ALARM_R

Name: ALARM_R Register
Description: This register reads the current alarm value of AON_WDT.
Base Address: 0x4000A700
Offset: 0x50
Reset Value: 0x00000000

表 364 ALARM_R
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R	0x0	Reserved bits
15:0	VAL	RO	0x0	Current internal alarm value of the AON WDT