Advanced Encryption Standard (AES)

表 476 AES module standard

Document Code	Name of Standard
FIPS PUB 197	Advanced Encryption Standard (AES)

The AES co-processor encrypts or decrypts data, using an algorithm and implementation fully compliant with the AES defined in Federal Information Processing Standards (FIPS) publication 197. In the SoC, the AES module is a crypto engine inside the Bluetooth LE Core, so that its operation should comply with the rules of the Bluetooth LE Core.

Electronic Codebook (ECB) and Cipher Block Chaining (CBC) are supported for key size of 128 bits. Due to the feature of block cipher of AES, the data to be encrypted or decrypted requires an integer multiple of 16 bytes. AES calculation process needs to be performed in interrupt mode.

It should be noticed that the ECB mode and the CBC mode are mutually exclusive so that the two modes cannot be used at the same time. When an Encrypted Link Layer event has to be processed, it is possible that Event Controller /Packet Controller may require AES to respond to the event while the calculation is in process. In this case, the current encryption/decryption process will stop if the processing of the event has a higher priority.

AES-128 can be used by software which stores the block to cipher/decipher at AESPTR address in the exchange memory. The block size to cipher/decipher is always considered equal to 16 bytes.

The AES can be switched into ECB or CBC mode by configuring AESCNTL.AES_ALG_MODE.

The 128-bit symmetric key needs to be set in the AESKEYx_x registers. If the AES works in CBC mode, the initialization vector needs to be set in the CBC_AES_IV_x registers. AESCNTL.CBC_AES_FIRST_BLOCK_IND is used to configure whether the block is the first block in CBC mode.

Once the settings complete, the AES can be started with the cipher/decipher mode set in AESCNTL.AES_MODE, and a 1 written in AESCNTL.AES_START.

Upon normal termination, the software will receive a ble_crypt_irq interrupt. The ciphered/deciphered data can be found at AESPTR+16 address. When the encryption/decryption process is till normal termination, the AES will automatically reset the AESCNTL.AES_START bit.

• Name: AES Controller Register

• Description: This register acts as a controller register for AES.

• Base Address: 0x400E0000

• Offset: 0xB0

• Reset Value: 0x00000000

表 477 AES Controller Register

Bits	Field Name	RW	Reset	Description
31:2	RSVD	R		Reserved bits
3	CBC_AES_FIRST_BLOCK_IND	RW	0x0	Indicate AES-CBC mode first block; first block is set to 1, and others set to 0.
2	AES_ALG_MODE	RW	0x0	AES algorithm mode Value: 0x0: ECB mode 0x1: CBC mode
1	AES_MODE	RW	0x0	AES operation mode Value: 0x0: Cipher mode 0x1: Decipher mode
0	AES_START	RW	0x0	Writing a 1 starts AES-128 ciphering/deciphering process. This bit is reset once the process is finished.

• Name: AES Key 31_0 Register

• Description: This register is a 32-bit buffer for the key[31:0] for AES.

• Base Address: 0x400E0000

• Offset: 0xB4

• Reset Value: 0x00000000

表 478 AES Key 31_0 Register

Bits	Field Name	RW	Reset	Description
31:0	AESKEY31_0	RW	0x0	AES encryption 128-bit key. Bit 31 down to 0

• Name: AES Key 63_32 Register

• Description: This register is a 32-bit buffer for the key[63:32] for AES.

• Base Address: 0x400E0000

• Offset: 0xB8

• Reset Value: 0x00000000

表 479 AES Key 63_32 Register

Bits	Field Name	RW	Reset	Description
31:0	AESKEY63_32	RW	0x0	AES encryption 128-bit key. Bit 63 down to 32

• Name: AES Key 95_64 Register

• Description: This register is a 32-bit buffer for the key[95:64] for AES.

• Base Address: 0x400E0000

• Offset: 0xBC

• Reset Value: 0x00000000

表 480 AES Key 95_64 Register

Bits	Field Name	RW	Reset	Description
31:0	AESKEY95_64	RW	0x0	AES encryption 128-bit key. Bit 95 down to 64

• Name: AES Key 127_96 Register

• Description: This register is a 32-bit buffer for the key[127:96] for AES.

• Base Address: 0x400E0000

• Offset: 0xC0

• Reset Value: 0x00000000

表 481 AES Key 127_96 Register

Bits	Field Name	RW	Reset	Description
31:0	AESKEY127_96	RW	0x0	AES encryption 128-bit key. Bit 127 down to 96

• Name: AES Pointer Register

• Description: This register acts as a memory offset pointer register for AES.

• Base Address: 0x400E0000

• Offset: 0xC4

• Reset Value: 0x00000000

表 482 AES Pointer Register

Bits	Field Name	RW	Reset	Description
31:14	RSVD	R		Reserved bits
13:0	AESPTR	RW	0x0	Pointer to the memory zone where the block to cipher/decipher using AES-128 is stored.

• Name: AES CBC IV 0 Register

• Description: This register is a 32-bit buffer for the Initialization Vector (IV) [31:0] for AES CBC mode.

• Base Address: 0x400E0000

• Offset: 0x210

• Reset Value: 0x00000000

表 483 AES CBC IV 0 Register

Bits	Field Name	RW	Reset	Description
31:0	CBC_AES_IV_0	RW	0x0	AES CBC mode IV. Bit 31 down to bit 0

• Name: AES CBC IV 1 Register

• Description: This register is a 32-bit buffer for the Initialization Vector (IV) [63:32] for AES CBC mode.

• Base Address: 0x400E0000

• Offset: 0x214

• Reset Value: 0x00000000

表 484 AES CBC IV 1 Register

Bits	Field Name	RW	Reset	Description
31:0	CBC_AES_IV_1	RW	0x0	AES CBC mode IV. Bit 63 down to bit 32

• Name: AES CBC IV 2 Register

• Description: This register is a 32-bit buffer for the Initialization Vector(IV) [95:64] for AES CBC mode.

• Base Address: 0x400E0000

• Offset: 0x218

• Reset Value: 0x00000000

表 485 AES CBC IV 2 Register

Bits	Field Name	RW	Reset	Description
31:0	CBC_AES_IV_2	RW	0x0	AES CBC mode IV. Bit 95 down to bit 64

• Name: AES CBC IV 3 Register

• Description: This register is a 32-bit buffer for the Initialization Vector (IV) [127:96] for AES CBC mode.

• Base Address: 0x400E0000

• Offset: 0x21C

• Reset Value: 0x00000000

表 486 AES CBC IV 3 Register

Bits	Field Name	RW	Reset	Description
31:0	CBC_AES_IV_3	RW	0x0	AES CBC mode IV. Bit 127 down to bit 96