GPIO
Introduction
The device has up to 14 individually configurable GPIOs that can serve as peripherals or digital input/output.
Main Features
- All I/Os can retain their output levels when the system enters sleep mode.
- I/O default state is input mode with pull-down.
- All I/Os (except MSIO_0–MSIO_9) can be configured as being triggered by high level, low level, rising edge, falling edge, or both edges.
- Configurable output drive strength: four drive strengths and two slew rate options. The fast slew rate should be used when speed or timing is a concern; the slow slew rate is used to reduce the switching noise.
- All pins can be individually mapped to interface blocks for layout flexibility.
Functional Description
The 14 digital GPIOs can be used:
- For general-purpose input/output.
- To multiplex different peripherals on different output pins of the package.
- To multiplex debug signals from different blocks of the SoC.
A functional drawing of the GPIO pads is provided in the following figure. The digital GPIO pads can be configured to set direction, enable pull-up/pull-down resistors, and enable output retention. GPIOs can also be read or written by firmware for applications that need direct access through the GPIO registers.
The general rule for enabling the on-chip pull-up/pull-down resistors is as follows:
-
If a GPIO is unused, enable the pull-down resistor.
-
If a GPIO is configured as an output, disable the pull-up/pull-down resistor. However, if disabling the output causes a high impedance state, enable the pull-up or pull-down resistor during this period.
-
If a GPIO is used as an input and is being actively driven high or low by an external device, disable the pull-up/pull-down resistor (the same applies when there is an external pull-up/pull-down resistor on the board. In this case, the on-chip resistor should always be disabled). However, if the external device driving the input ever goes to a high impedance state, a pull-up or pull-down resistor must be enabled during this period.
Registers
PAD_IE_AUTO_EN
- Name: Pad auto Input Enable Control Register
- Description: This register enables/disables auto pad input.
- Base Address: 0x4000E900
- Offset: 0x28
- Reset Value: 0x0000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
31:20 |
RSVD |
R |
Reserved bits |
|
2 |
MSIO_IE_AUTO_EN |
RW |
0x0 |
Enable/Disable DPAD auto input. Value:
|
1 |
AON_IE_AUTO_EN |
RW |
0x0 |
Enable/Disable AON pad auto input. Value:
|
0 |
DPAD_IE_AUTO_EN |
RW |
0x0 |
Enable/Disable MSIO auto input. Value:
|
DPAD_IE_BUS
- Name: GPIO Input Enable Register
- Description: This register enables a GPIO as input.
- Base Address: 0x4000E900
- Offset: 0x2C
- Reset Value: 0x000FFFFF
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:20 |
RSVD |
R |
Reserved bits |
|
| 19:0 |
IE |
RW |
0xFFFFF |
Enable l/O inputs to GPIO_0–GPIO_13 Value:
|
DPAD_PE_BUS
- Name: GPIO Pull-Up/Down Resistor Enable Register
- Description: This register decides whether to use pull-up/down resistors.
- Base Address: 0x4000E900
- Offset: 0x30
- Reset Value: 0x00003FFF
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:20 |
RSVD |
R |
Reserved bits |
|
| 19:0 |
PE |
RW |
0x3FFF |
Resistor enable control of GPIO_0–GPIO_13 Value:
|
DPAD_PS_BUS
- Name: GPIO Resistor Type Control Register
- Description: This register sets the resistor type to either pull-up or pull-down.
- Base Address: 0x4000E900
- Offset: 0x34
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:20 |
RSVD |
R |
Reserved bits |
|
| 19:0 |
PS |
RW |
0x0 |
Resistor type of GPIO_0–GPIO_13 Value:
|
DPAD_IS_BUS
- Name: GPIO Input Type Control Register
- Description: This register sets the input type.
- Base Address: 0x4000E900
- Offset: 0x38
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:20 |
RSVD |
R |
Reserved bits |
|
| 19:0 |
IS |
RW |
0x0 |
Input type of GPIO_0–GPIO_13 Value:
|
DPAD_SR_BUS
- Name: GPIO Slew Rate Control Register
- Description: This register sets the slew rate of GPIOs.
- Base Address: 0x4000E900
- Offset: 0x3C
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:20 |
RSVD |
R |
Reserved bits |
|
| 19:0 |
SR |
RW |
0x0 |
Resistor type of GPIO_0–GPIO_13 Value:
|
DPAD_DS0_BUS
- Name: GPIO Output Driver Strength Type Control Register
- Description: This register sets the output driver strength.
- Base Address: 0x4000E900
- Offset: 0x40
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:20 |
RSVD |
R |
Reserved bits |
|
| 19:0 |
DS0 |
RW |
0x0 |
Output drive strength (high bit) Value:
|
DPAD_DS1_BUS
- Name: GPIO Output Driver Strength Type Control Register
- Description: This register sets the output driver strength.
- Base Address: 0x4000E900
- Offset: 0x44
- Reset Value: 0x000FFFFF
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:20 |
RSVD |
R |
Reserved bits |
|
| 19:0 |
DS1 |
RW |
0xFFFFF |
Output drive strength (low bit) Value:
|
The drive strengths of GPIO0 can be configured as follows:
- DPAD_DS0_BUS[0]: DPAD_DS1_BUS[0] = 1:1, output drive strength is 12 mA.
- DPAD_DS0_BUS[0]: DPAD_DS1_BUS[0] = 1:0, output drive strength is 8 mA.
- DPAD_DS0_BUS[0]: DPAD_DS1_BUS[0] = 0:1, output drive strength is 4 mA.
- DPAD_DS0_BUS[0]: DPAD_DS1_BUS[0] = 0:0, output drive strength is 2 mA.
DATA
- Name: GPIO Data Value Register
- Description: This register contains the input data and can write it to the data output register.
- Base Address: 0x40010000
- Offset: 0x0000
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:16 |
RSVD |
R |
Reserved bits |
|
| 15:0 |
DATA |
RW |
0x0 |
Data value [15:0]: Read: Read the value that is sampled at pin. Write: Write the field to the DATA_OUT register. |
GPIO includes GPIOA (GPIO_0–GPIO_13) in SDK.
DATA_OUT
- Name: GPIO Data Output Register
- Description: This register contains the output data.
- Base Address: 0x40010000
- Offset: 0x0004
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:16 |
RSVD |
R |
Reserved bits |
|
| 15:0 |
DATA_OUT |
RW |
0x0 |
Data output register value [15:0]: Read: current value of data output register Write: to data output register |
OUTENSET
- Name: GPIO Output Enable Register
- Description: This register is used to enable the GPIO as output.
- Base Address: 0x40010000
- Offset: 0x0010
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:16 |
RSVD |
R |
Reserved bits |
|
| 15:0 |
EN |
RW |
0x0 |
Output enable set [15:0]: Read:
Write:
|
OUTENCLR
- Name: GPIO Output Enable Clear Register
- Description: This register is used to disable output bit.
- Base Address: 0x40010000
- Offset: 0x0014
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:16 |
RSVD |
R |
Reserved bits |
|
| 15:0 |
CLR |
RW |
0x0 |
Output enable clear [15:0]: Read:
Write:
|
INTENSET
- Name: GPIO Interrupt Enable Register
- Description: This register is used to enable GPIO interrupt.
- Base Address: 0x40010000
- Offset: 0x0020
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:16 |
RSVD |
R |
Reserved bits |
|
| 15:0 |
EN |
RW |
0x0 |
Interrupt enable set [15:0]: Read:
Write:
|
INTENCLR
- Name: GPIO Interrupt Enable Clear Register
- Description: This register is used to disable GPIO interrupt.
- Base Address: 0x40010000
- Offset: 0x0024
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:16 |
RSVD |
R |
Reserved bits |
|
| 15:0 |
CLR |
RW |
0x0 |
Interrupt enable clear [15:0]: Read:
Write:
|
INTTYPESET
- Name: GPIO Interrupt Type Enable Register
- Description: This register is used to set GPIO interrupt type.
- Interrupt type is 0 and interrupt polarity is 0: low-level trigger interrupt
- Interrupt type is 0 and interrupt polarity is 1: high-level trigger interrupt
- Interrupt type is 1 and interrupt polarity is 0: falling edge trigger interrupt
- Interrupt type is 1 and interrupt polarity is 1: rising edge trigger interrupt
- Base Address: 0x40010000
- Offset: 0x0028
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:16 |
RSVD |
R |
Reserved bits |
|
| 15:0 |
EN |
RW |
0x0 |
Interrupt type set [15:0]: Read:
Write:
|
INTTYPECLR
- Name: GPIO Interrupt Type Clear Register
- Description: This register is used to disable GPIO interrupt type.
- Base Address: 0x40010000
- Offset: 0x002C
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:16 |
RSVD |
R |
Reserved bits |
|
| 15:0 |
CLR |
RW |
0x0 |
Interrupt type clear [15:0]: Read:
Write:
|
INTPOLSET
- Name: GPIO Interrupt Polarity Enable Register
- Description: This register is used to enable GPIO interrupt polarity.
- Base Address: 0x40010000
- Offset: 0x0030
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:16 |
RSVD |
R |
Reserved bits |
|
| 15:0 |
EN |
RW |
0x0 |
Polarity configuration [15:0]: Read:
Write:
|
INTPOLCLR
- Name: GPIO Interrupt Polarity Disable Register
- Description: This register is used to disable GPIO interrupt polarity.
- Base Address: 0x40010000
- Offset: 0x0034
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:16 |
RSVD |
R |
Reserved bits |
|
| 15:0 |
CLR |
RW |
0x0 |
Polarity configuration [15:0]: Read:
Write:
|
INTSTAT
- Name: GPIO IRQ Status Register
- Description: This register contains GPIO interrupt status and is used to clear the interrupt request.
- Base Address: 0x40010000
- Offset: 0x0038
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:16 |
RSVD |
R |
Reserved bits |
|
| 15:0 |
STAT_CLR |
RW |
0x0 |
Write one to clear interrupt request: Read: [15:0] IRQ status register Write:
|
INTDBESET
- Name: GPIO_REG_INTDBESET Register
- Description: This register is used to set the double-edge interrupt enable bit (which means that both falling edge and rising edge will get the interrupt).
- Base Address: 0x40010000
- Offset: 0x0040
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:16 |
RSVD |
R |
Reserved bits |
|
| 15:0 |
EN |
RW |
0x0 |
Read:
Write:
|
INTDBECLR
- Name: GPIO_REG_INTDBECLR Register
- Description: This register is used to clear the double-edge interrupt enable bit (which means that both falling edge and rising edge will get the interrupt).
- Base Address: 0x40010000
- Offset: 0x0044
- Reset Value: 0x00000000
| Bits | Field Name | RW | Reset | Description |
|---|---|---|---|---|
| 31:16 |
RSVD |
R |
Reserved bits |
|
| 15:0 |
CLR |
RW |
0x0 |
Write 1: Clear the double-edge interrupt enable bit (which means that both falling edge and rising edge will get the interrupt). Write 0: No effect Read back 1: Enable the double-edge interrupt. Read back 0: Disable the double-edge interrupt. |
Electrical Specifications
The electrical parameters for the GPIO_0–GPIO_13 are as follows:
| Parameter | Description | Min. | Typ. | Max. | Unit |
|---|---|---|---|---|---|
| VIH | Input high voltage | VDDIO x 0.7 | VDDIO | V | |
| VIL | Input low voltage | VSS | VDDIO x 0.3 | V | |
| VOH,L | Output high voltage, 4 mA, VDDIO ≥ 2.0 V | VDDIO - 0.4 | VDDIO | V | |
| VOH,M | Output high voltage, 4 mA, VDDIO ≥ 2.5 V | VDDIO - 0.4 | VDDIO | V | |
| VOH,H | Output high voltage, 4 mA, VDDIO ≥ 3 V | VDDIO - 0.4 | VDDIO | V | |
| VOL,L | Output low voltage, 4 mA, VDDIO ≥ 2.0 V | VSS | VSS + 0.4 | V | |
| VOL,M | Output low voltage, 4 mA, VDDIO ≥ 2.5 V | VSS | VSS + 0.4 | V | |
| VOL,H | Output low voltage, 4 mA, VDDIO ≥ 3 V | VSS | VSS + 0.4 | V | |
| IOL,L | Current at VSS+0.4 V, output set low, VDDIO ≥ 2.0 V | 2 | 12 | mA | |
| IOL,M | Current at VSS+0.4 V, output set low, VDDIO ≥ 2.5 V | 2 | 12 | mA | |
| IOH,L | Current at VDDIO-0.4 V, output set high, VDDIO ≥ 2.0 V | 2 | 12 | mA | |
| IOH,M | Current at VDDIO-0.4 V, output set high, VDDIO ≥ 2.5 V | 2 | 12 | mA | |
| tRF,9pF | Rise time, 10%–90%, 9 pF load | 1.6 | 13 | ns | |
| tRF,9pF | Fall time, 10%–90%, 9 pF load | 1.9 | 14.2 | ns | |
| RPU | Pull-up resistance | 12 | 20 | 32 | kΩ |
| RPD | Pull-down resistance | 12 | 20 | 32 | kΩ |
| CPAD | Pad capacitance | 5 | pF |
