Dual Timer

Introduction

The Dual Timer module consists of two programmable down counters (32-bit or 16-bit) that can generate interrupts when they reach 0. I/O control function without going through interrupt handler is supported in order to meet the requirements of application scenarios that demand low latency response.

Because the Dual-Timer is in the MCU Subsystem domain, Dual-Timer interrupt is not available during sleep, and the running Dual-Timer will not prevent the MCU from sleeping.

Main Features

Two 32-bit or 16-bit counters
One of the following timer modes:
- Periodic
- One-shot
- Free-running
3-channel I/O control interface for each dual timer instance supports I/O set, reset and toggle.
One I/O control channel supports up to five compare events, including START, STOP, PERIOD and two custom COUNT events.
Flexible and configurable interrupts for all compare events in I/O control function.
The clock source of the Dual Timer follows the system clock
Dual Timer has a prescaler that can divide down the enabled timer clock rate by a factor of 1, 16, or 256.
Dual Timer supports the specified number of cycles to stop counting.
Dual Timer pauses when the MCU is suspended.

Functional Description

Counter

In Dual Timer, both of the counters are defined by default, and they can be defined as either 16-bit or 32-bit down counter. For each counter, the following operational modes are available:

Free-running mode
The counter wraps after reaching zero, and continues to count down from the maximum value (0xFFFFFFFF). This is the default mode.
Periodic mode
The counter generates an interrupt at a fixed interval, reloading the original value after wrapping past zero values.
One-shot mode
The counter generates an interrupt once. When the counter reaches 0, it halts until you reprogram it.

The RELOAD value only represents the count-down number of timers. To configure a specific duration (for example, µs, ms, or s), use the following formula:

where PRE stands for prescaled coefficient.

When the value of the RELOAD register is configured to 0, no count and no interrupt are generated.

Dual timer supports background reload function in periodic mode. If the BG_LOAD register is configured with a value, the Dual Timer will restart counting down with the BG_LOAD value after the current counting cycle is completed. If BG_LOAD value is set before Dual Timer is initialized, the BG_LOAD value will become invalid after the Dual Timer is initialized with the RELOAD value.

Dual timer supports one-time background reload function in periodic mode. If the TP_LOAD register is configured with a value, the Dual Timer will start counting down one-time with the TP_LOAD value after the current counting cycle is completed. When the BG_LOAD and TP_LOAD registers are configured at the same time, the dual timer will respond to the TP_LOAD register first.

Dual Timer supports the specified number of cycles to stop counting in periodic mode. If the PERIOD_COUNT register is configured with a value, the Dual Timer will stop counting after the specified number of cycles are completed. The value is valid when it is greater than 1. The PERIOD_COUNT register is only valid when one of the I/O control channels is enabled.

I/O Control

The dual timer supports I/O control function without going through interrupt handler. Each of the instance supports three channels with up to five compare events.

I/O is muxed to dual timer in order to implement I/O control function.
I/O initial state can be defined through the IO_INIT_SET register before the I/O control channel is enabled.
There are up to five compare events for I/O control. When the dual timer starts counting, the start event will trigger the channel I/O action. When the counter value reaches zero, the PERIOD event will trigger the channel I/O action. When the dual timer stops counting, the STOP event will trigger the channel I/O action. Each channel has two custom compare values which can be configured in COUNT_x1IO and COUNT_x2IO registers. When the counter value reaches the compare value, the IOx_C1 and IOx_C2 events will trigger the channel I/O action. Compare value greater than reload value will not trigger an interrupt or IO control action.
I/O action supports I/O set, reset and toggle.
Flexible and configurable interrupts for all compare events in I/O control function.
Channel I/O will trigger a PERIOD event action and a STOP event action in sequence at the end of the counting in one-shot mode.

For example, the I/O action timing diagram of I/O control function using dual timer is shown in the figure below.

Registers

RELOAD

Name: Dual Timer Reload Register
Description: This register contains the value from which the counter is to decrease. The count is immediately restarted from the new RELOAD value.
Base Address: 0x40002000
Offset: 0x00 + x*0x80
Reset Value: 0x00

Note:

*x is used to identify the counter of the Dual Timer Module. The “x” can be 0 or 1.

表 308 RELOAD
Bits	Field Name	RW	Reset	Description
31:0	RELOAD	RW	0x0	Reload value. Write to this register sets the current value.

VALUE

Name: Dual Timer Current Value Register
Description: This register provides the current count value of the decrementing counter.
Base Address: 0x40002000
Offset: 0x04 + x*0x80
Reset Value: 0xFFFFFFFF

表 309 VALUE
Bits	Field Name	RW	Reset	Description
31:0	VALUE	RO	0xFFFFFFFF	Current count value

CTRL

Name: Dual Timer Control Register
Description: This register enables the software to control the Dual Timer.
Base Address: 0x40002000
Offset: 0x08 + x*0x80
Reset Value: 0x20

表 310 CTRL
Bits	Field Name	RW	Reset	Description
31:21	RSVD	R		Reserved bits
20	IOC_ACT_C2_INTEN	RW	0x0	Interrupt when timer value meets COUNT_C2IO Value: 0x0: disabled 0x1: enabled
19	IOC_ACT_C1_INTEN	RW	0x0	Interrupt when timer value meets COUNT_C1IO Value: 0x0: disabled 0x1: enabled
18	IOB_ACT_C2_INTEN	RW	0x0	Interrupt when timer value meets COUNT_B2IO Value: 0x0: disabled 0x1: enabled
17	IOB_ACT_C1_INTEN	RW	0x0	Interrupt when timer value meets COUNT_B1IO Value: 0x0: disabled 0x1: enabled
16	ACT_STOP_INTEN	RW	0x0	Interrupt when timer stop Value: 0x0: disabled 0x1: enabled
15	ACT_PERIOD_INTEN	RW	0x0	Interrupt when timer value meets 0 Value: 0x0: disabled 0x1: enabled
14	IOA_ACT_C2_INTEN	RW	0x0	Interrupt when timer value meets COUNT_A2IO Value: 0x0: disabled 0x1: enabled
13	IOA_ACT_C1_INTEN	RW	0x0	Interrupt when timer value meets COUNT_A1IO Value: 0x0: disabled 0x1: enabled
12	ACT_START_INTEN	RW	0x0	Interrupt when timer start Value: 0x0: disabled 0x1: enabled
11	RSVD	R		Reserved bits
10	IOC	RW	0x0	Channel C I/O Control enable Value: 0x0: disabled 0x1: enabled
9	IOB	RW	0x0	Channel B I/O Control enable Value: 0x0: disabled 0x1: enabled
8	IOA	RW	0x0	Channel A I/O Control enable Value: 0x0: disabled 0x1: enabled
7	EN	RW	0x0	Timer enable Value: 0x0: Timer disabled; default 0x1: Timer enabled
6	MODE	RW	0x0	Timer mode Value: 0x0: Timer is in free-running mode; default 0x1: Timer is in periodic mode
5	INTEN	RW	0x1	Interrupt enable Value: 0x0: Timer interrupt disabled 0x1: Timer interrupt enabled; default
4	RSVD	R		Reserved bits
3:2	PRE	RW	0x0	Prescale bits Value: 0x00: 0 stage of prescale, clock is divided by 1; default 0x01: 4 stages of prescale, clock is divided by 16 0x10: 8 stages of prescale, clock is divided by 256 0x11: Undefined. Do not use this value.
1	SIZE	RW	0x0	Select 16-bit or 32-bit counter operation: Value: 0x0: 16-bit counter; default 0x1: 32-bit counter
0	ONESHOT	RW	0x0	Select wrap mode or one-shot mode: Value: 0x0: Wrap mode; default 0x1: One-shot mode

INTCLR

Name: Dual Timer Interrupt Clear Register
Description: Any write to the INTCLR register clears the interrupt output from the counter.
Base Address: 0x40002000
Offset: 0x0C + x*0x80
Reset Value: 0x00

表 311 INTCLR
Bits	Field Name	RW	Reset	Description
31:0	CLR	WO	0x0	Clear the Dual-Timer interrupt event.

RAW_INTSTAT

Name: Dual Timer Raw Interrupt Status Register
Description: The RAW_INTSTAT register indicates the raw interrupt status from the counter.
Base Address: 0x40002000
Offset: 0x10 + x*0x80
Reset Value: 0x00

表 312 RAW_INTSTAT
Bits	Field Name	RW	Reset	Description
31:1	RSVD	R		Reserved bits
0	RIS_RTI	RO	0x0	Raw interrupt status from the counter

INTSTAT

Name: Dual-Timer interrupt enable status register
Description: The INTSTAT register indicates the masked interrupt status from the counter.
Base Address: 0x40002000
Offset: 0x14 + x*0x80
Reset Value: 0x00

表 313 INTSTAT
Bits	Field Name	RW	Reset	Description
31:10	RSVD	R		Reserved bits
9	IOC_ACT_C2	R	0x0	Interrupt status when timer value meets to COUNT_C2IO
8	IOC_ACT_C1	R	0x0	Interrupt status when timer value meets to COUNT_C1IO
7	IOB_ACT_C2	R	0x0	Interrupt status when timer value meets to COUNT_B2IO
6	IOB_ACT_C1	R	0x0	Interrupt status when timer value meets to COUNT_B1IO
5	ACT_STOP	R	0x0	Interrupt status when timer stop.
4	ACT_PERIOD	R	0x0	Interrupt status when timer value meets to 0
3	IOA_ACT_C2	R	0x0	Interrupt status when timer value meets to COUNT_A2IO
2	IOA_ACT_C1	R	0x0	Interrupt status when timer value meets to COUNT_A1IO
1	ACT_START	R	0x0	Interrupt status when timer start.
0	ISR_TI	RO	0x0	Enable interrupt status from the counter.

BG_LOAD

Name: Dual-Timer background reload register
Description: When the BG_LOAD value is set, the counter will count down again from the BG_LOAD value after completing the current counting cycle.
Base Address: 0x40002000
Offset: 0x18 + x*0x80
Reset Value: 0x00

表 314 BG_LOAD
Bits	Field Name	RW	Reset	Description
31:0	BL	RW	0x0	The BG_LOAD does not cause the counter to immediately restart from the new value.

COUNT_A1IO

Name: Dual-Timer Channel A Count 1 register
Description: This register indicates the count 1 value for channel A I/O Control.
Base Address: 0x40002000
Offset: 0x1C + x*0x80
Reset Value: 0xFFFFFFFF

表 315 COUNT_A1IO
Bits	Field Name	RW	Reset	Description
31:0	COUNT_A1IO	RW	0xFFFFFFFF	When timer value meet this value, the channel A will act.

COUNT_A2IO

Name: Dual-Timer Channel A Count 2 register
Description: This register indicates the count 2 value for channel A I/O Control.
Base Address: 0x40002000
Offset: 0x20 + x*0x80
Reset Value: 0xFFFFFFFF

表 316 COUNT_A2IO
Bits	Field Name	RW	Reset	Description
31:0	COUNT_A2IO	RW	0xFFFFFFFF	When timer value meet this value, the channel A will act.

COUNT_B1IO

Name: Dual-Timer Channel B Count 1 register
Description: This register indicates the count 1 value for channel B I/O Control.
Base Address: 0x40002000
Offset: 0x24 + x*0x80
Reset Value: 0xFFFFFFFF

表 317 COUNT_B1IO
Bits	Field Name	RW	Reset	Description
31:0	COUNT_B1IO	RW	0xFFFFFFFF	When timer value meet this value, the channel B will act.

COUNT_B2IO

Name: Dual-Timer Channel B Count 2 register
Description: This register indicates the count 2 value for channel B I/O Control.
Base Address: 0x40002000
Offset: 0x28 + x*0x80
Reset Value: 0xFFFFFFFF

表 318 COUNT_B2IO
Bits	Field Name	RW	Reset	Description
31:0	COUNT_B2IO	RW	0xFFFFFFFF	When timer value meet this value, the channel B will act.

COUNT_C1IO

Name: Dual-Timer Channel C Count 1 register
Description: This register indicates the count 1 value for channel C I/O Control.
Base Address: 0x40002000
Offset: 0x2C + x*0x80
Reset Value: 0xFFFFFFFF

表 319 COUNT_C1IO
Bits	Field Name	RW	Reset	Description
31:0	COUNT_C1IO	RW	0xFFFFFFFF	When timer value meet this value, the channel C will act.

COUNT_C2IO

Name: Dual-Timer Channel C Count 2 register
Description: This register indicates the count 2 value for channel C I/O Control.
Base Address: 0x40002000
Offset: 0x30 + x*0x80
Reset Value: 0xFFFFFFFF

表 320 COUNT_C2IO
Bits	Field Name	RW	Reset	Description
31:0	COUNT_C2IO	RW	0xFFFFFFFF	When timer value meet this value, the channel C will act.

IO_ACT_CTRL

Name: Dual-Timer I/O action control register
Description: This register enables the software to control I/O action.
Base Address: 0x40002000
Offset: 0x34 + x*0x80
Reset Value: 0x00

表 321 IO_ACT_CTRL
Bits	Field Name	RW	Reset	Description
31:30	RSVD	R		Reserved bits
29:28	IOC_ACT_CTRL_STOP	RW	0x0	Channel C action when timer stop Value: 0x0: do nothing 0x1: io set 0x2: io reset 0x3: io toggle
27:26	IOC_ACT_CTRL_PERIOD	RW	0x0	Channel C action when timer meets 0 Value: 0x0: do nothing 0x1: io set 0x2: io reset 0x3: io toggle
25:24	IOC_ACT_CTRL_C2	RW	0x0	Channel C action when timer meets COUNT_C2IO Value: 0x0: do nothing 0x1: io set 0x2: io reset 0x3: io toggle
23:22	IOC_ACT_CTRL_C1	RW	0x0	Channel C action when timer meets COUNT_C1IO Value: 0x0: do nothing 0x1: io set 0x2: io reset 0x3: io toggle
21:20	IOC_ACT_CTRL_START	RW	0x0	Channel C action when timer start Value: 0x0: do nothing 0x1: io set 0x2: io reset 0x3: io toggle
19:18	IOB_ACT_CTRL_STOP	RW	0x0	Channel B action when timer stop Value: 0x0: do nothing 0x1: io set 0x2: io reset 0x3: io toggle
17:16	IOB_ACT_CTRL_PERIOD	RW	0x0	Channel B action when timer meets 0 Value: 0x0: do nothing 0x1: io set 0x2: io reset 0x3: io toggle
15:14	IOB_ACT_CTRL_C2	RW	0x0	Channel B action when timer meets COUNT_B2IO Value: 0x0: do nothing 0x1: io set 0x2: io reset 0x3: io toggle
13:12	IOB_ACT_CTRL_C1	RW	0x0	Channel B action when timer meets COUNT_B1IO Value: 0x0: do nothing 0x1: io set 0x2: io reset 0x3: io toggle
11:10	IOB_ACT_CTRL_START	RW	0x0	Channel B action when timer start Value: 0x0: do nothing 0x1: io set 0x2: io reset 0x3: io toggle
9:8	IOA_ACT_CTRL_STOP	RW	0x0	Channel A action when timer stop Value: 0x0: do nothing 0x1: io set 0x2: io reset 0x3: io toggle
7:6	IOA_ACT_CTRL_PERIOD	RW	0x0	Channel A action when timer meets 0 Value: 0x0: do nothing 0x1: io set 0x2: io reset 0x3: io toggle
5:4	IOA_ACT_CTRL_C2	RW	0x0	Channel A action when timer meets COUNT_A2IO Value: 0x0: do nothing 0x1: io set 0x2: io reset 0x3: io toggle
3:2	IOA_ACT_CTRL_C1	RW	0x0	Channel A action when timer meets COUNT_A1IO Value: 0x0: do nothing 0x1: io set 0x2: io reset 0x3: io toggle
1:0	IOA_ACT_CTRL_START	RW	0x0	Channel A action when timer start Value: 0x0: do nothing 0x1: io set 0x2: io reset 0x3: io toggle

IO_INIT_SET

Name: Dual-Timer I/O initial control register
Description: This register enables the software to control I/O initial state.
Base Address: 0x40002000
Offset: 0x38 + x*0x80
Reset Value: 0x00

表 322 IO_INIT_SET
Bits	Field Name	RW	Reset	Description
31:3	RSVD	R		Reserved bits
2	IOC_ACT_INIT	RW	0x0	Set channel C initial value when CTRL_IOC is disabled. Value: 0x0: reset 0x1: set
1	IOB_ACT_INIT	RW	0x0	Set channel B initial value when CTRL_IOB is disabled. Value: 0x0: reset 0x1: set
0	IOA_ACT_INIT	RW	0x0	Set channel A initial value when CTRL_IOA is disabled. Value: 0x0: reset 0x1: set

TP_LOAD

Name: Dual-Timer one-time reload register
Description: When the TP_LOAD value is set, the counter will count down again from the TP_LOAD value after completing the current counting cycle for one cycle.
Base Address: 0x40002000
Offset: 0x3C + x*0x80
Reset Value: 0x00

表 323 TP_LOAD
Bits	Field Name	RW	Reset	Description
31:0	TP_LOAD	RW	0x0	Used to reload the counter when Periodic mode/io action mode is enabled, and the current count reaches 0. The value is only invalid one time. When the timer reloads the value, the register will be cleared automatically.

PERIOD_COUNT

Name: Dual-Timer period count register
Description: This register indicates the period count in period mode.
Base Address: 0x40002000
Offset: 0x4C + x*0x80
Reset Value: 0x00

表 324 PERIOD_COUNT
Bits	Field Name	RW	Reset	Description
31:16	RSVD	R		Reserved bits
15:0	PERIOD_COUNT	RW	0x0	Set dual timer's period count in period mode. The value is valid when the value is greater than 1.

IO_BLE_INTCLR

Name: Dual Timer I/O Control Interrupt Clear Register
Description: Any write to the IO_BLE_INTCLR register clears the interrupt of I/O control function.
Base Address: 0x40002000
Offset: 0x50 + x*0x80
Reset Value: 0x00

表 325 IO_BLE_INTCLR
Bits	Field Name	RW	Reset	Description
31:12	RSVD	R		Reserved bits
11	IO_ACT_ALL_INTCLR	W	0x0	Write 1 to clear all io interrupt status.
10:9	RSVD	R		Reserved bits
8	IOC_ACT_C2_INTCLR	W	0x0	Write 1 to clear IOC_ACT_C2.
7	IOC_ACT_C1_INTCLR	W	0x0	Write 1 to clear IOC_ACT_C1.
6	IOB_ACT_C2_INTCLR	W	0x0	Write 1 to clear IOB_ACT_C2.
5	IOB_ACT_C1_INTCLR	W	0x0	Write 1 to clear IOB_ACT_C1.
4	ACT_STOP_INTCLR	W	0x0	Write 1 to clear ACT_STOP.
3	ACT_PERIOD_INTCLR	W	0x0	Write 1 to clear ACT_PERIOD.
2	IOA_ACT_C2_INTCLR	W	0x0	Write 1 to clear IOA_ACT_C2.
1	IOA_ACT_C1_INTCLR	W	0x0	Write 1 to clear IOA_ACT_C1.
0	ACT_START_INTCLR	W	0x0	Write 1 to clear ACT_START.